Patents Represented by Attorney Robert A. Walsh
  • Patent number: 8279687
    Abstract: A reduced bitline precharge level has been found to increase the SRAM Beta ratio, thus improving the stability margin. The precharge level is also supplied to Sense amplifier, write driver, and source voltages for control signals. In the sense amplifier, the lower precharge voltage compensates for performance loss in the bit-cell by operating global data-line drivers with increased overdrive. In the write driver, the reduced voltage improves the Bitline discharge rate, improves the efficiency of the negative boost write assist, and decreases the reliability exposure of transistors in the write path from negative boost circuit.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: October 2, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chad A. Adams, George M. Braceras, Daniel M Nelson, Harold Pilo, Vinod Ramadurai
  • Patent number: 7981731
    Abstract: A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: July 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: John A. Fifield, Russell J. Houghton, William R. Tonti
  • Patent number: 7914949
    Abstract: A method, a recording medium and an apparatus for testing a photomask are provided. In the disclosed method, a particular region of a photomask is selected, either from a physical instance of the photomask, or from the photomask as represented by a digital representation thereof. The particular region is then characterized by identifying a pattern type present in the particular region. A lithographic process stress condition is determined for the particular region, considering the pattern type, and thereafter, a result of lithographically patterning a feature is determined by simulating a photolithographic exposure, using the particular region of the photomask under the lithographic process stress condition. Then, it is decided whether the particular region of the photomask is acceptable based on the result of the simulated exposure only under the lithographic process stress condition.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventor: Jed H. Rankin
  • Patent number: 7704804
    Abstract: A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: April 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter
  • Patent number: 7688611
    Abstract: This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A reference match-line is provided to generate the timing for the search operation and provide the timing for the asynchronous application of the search data on the SLs. Additional noise reduction is achieved through the staggering of the search data application on the SLs through programmable delay elements.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: March 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Igor Arsovski, Rahul K. Nadkami, Reid A. Wistort
  • Patent number: 7515449
    Abstract: This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A reference match-line is provided to generate the timing for the search operation and provide the timing for the asynchronous application of the search data on the SLs. Additional noise reduction is achieved through the staggering of the search data application on the SLs through programmable delay elements.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: April 7, 2009
    Assignee: International Business Machines Corporation
    Inventors: Igor Arsovski, Rahul K. Nadkarni, Reid A. Wistort
  • Patent number: 7401278
    Abstract: A binary latch that operates as an edge-triggered flip-flop and which is LSSD-testable that comprises an edge triggered master. The binary latch comprises an edge triggered master flip-flop (2), with a clock input connected to the system clock (SYS_CLK), with a data input (DI) and with an output (DO), a level sensitive scan design (LSSD) slave latch (3), connected to the output (DO) of the master flip-flop (2), a NAND gate (4) with a first input (41) connected to the system clock (SYS_CLK), a second input (42) connected to a test input (TEST) and with an output (43) connected to the LSSD slave latch clock input (LSSD_clk).
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: July 15, 2008
    Assignee: International Business Machines Corporation
    Inventor: Peter Verwegen
  • Patent number: 7194670
    Abstract: Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate ā€œnā€ sets of CAD information which are then time-multiplexed to the embedded memory at a speed ā€œnā€ times faster than the BIST operating speed.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: March 20, 2007
    Assignee: International Business Machines Corp.
    Inventors: Jonathan R. Fales, Gregory J. Fredeman, Kevin W. Gorman, Mark D. Jacunski, Toshiaki Kirihata, Alan D. Norris, Paul C. Parries, Matthew R. Wordeman
  • Patent number: 7138326
    Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corp.
    Inventors: Harry D. Cox, David P. Daniel, Leonard J. Gardecki, Albert J. Gregoritsch, III, Ruth A. Machell Julianelle, Charles H. Keeler, Doris P. Pulaski, Mary A. Schaffer, David L. Smith, David J. Specht, Adolf E. Wirsing
  • Patent number: 6954389
    Abstract: To provide a dynamic semiconductor storage device featuring reduced power consumption and faster operation of a sense amplifier. The drain of a transistor N7 constituting an N-type sense amplifier NSAt is connected to a shared line SA, while the drain of a transistor N8 is connected to a shared line /SA. The drain of a transistor N9 constituting an N-type sense amplifier NSAb is connected to a shared line SA, while the drain of a transistor N10 is connected to a shared line /SA. The threshold voltages of transistors N7 to N10 range from 0.2V to 0.3V, which are lower than a threshold voltage of transistors P1 to P3. A supply voltage Vdd is applied to the gates of isolators BLIt and BLIb to clamp the supply voltage Vdd by the isolators BLIt and BLIb so as to set the internal voltage of an array to 0.8V, which is lower than the supply voltage Vdd by the threshold voltage of transistors N3 to N6.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: October 11, 2005
    Assignee: International Business Machines Corporation
    Inventor: Yutaka Nakamura
  • Patent number: 6927595
    Abstract: This invention teaches an apparatus and method for determining a more efficient quality assurance or reliability test screen without falsely rejecting, i.e., over stressing, short channel length devices during voltage stress test screening. Short channel lengths devices fabricated on a semiconductor wafer have a higher tendency to fail at voltage levels that would otherwise not harm long channel length devices. The failures, however, are not related to device defects. Protection to the more vulnerable devices is provided by determining the speed of the die prior to the voltage test screen, thus, segregating the devices based on operational speed performance. Next, a lower voltage is effectively applied during wafer probe test to the faster devices, which directly correspond to the population of short channel devices. A preferred measurement for device speed entails measuring the drain-to-source current of each FET, and dividing the resultant sum by the device gate channel width.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: August 9, 2005
    Assignee: International Business Machines Corporation
    Inventors: Roger W. Fleury, Jon A. Patrick
  • Patent number: 6888187
    Abstract: A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: May 3, 2005
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey S. Brown, David M. Fried, Edward J. Nowak, Beth Ann Rainey
  • Patent number: 6888714
    Abstract: A voltage supply bypass capacitor for use with a semiconductor integrated circuit chip or module comprising a ferroelectric dielectric having electromechanical properties designed to provide maximum losses at selected frequencies.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: May 3, 2005
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Shaw, W. David Pricer, Deborah A. Neumayer, John D. Baniecki, Robert B. Laibowitz
  • Patent number: 6880136
    Abstract: Defects in manufacturing of IC devices are analyzed by testing the devices for defects using results of LSSD technology to find at least one failing pattern that contains incorrect values. The failing latches are used as a starting point to trace back through combinational logic feeding the failing latches, until controllable latches are encountered. A decision is then made to continue the back tracing or not depending on whether the latter latches were clocked during the application of one of the failing patterns or not.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: April 12, 2005
    Assignee: International Business Machines Corporation
    Inventors: Leendert M. Huisman, Maroun Kassab, Leah M. P. Pastel
  • Patent number: 6864136
    Abstract: A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: March 8, 2005
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey S. Brown, David M. Fried, Edward J. Nowak, Beth Ann Rainey
  • Patent number: 6834003
    Abstract: A Content Addressable Memory (CAM) cell with PFET passgate SRAM cells which results in a smaller cell size because of the more balanced number of 8 PFET devices and 8 NFET devices. The PFET passgates allow the size of the SRAM cell pulldown devices to be reduced, and lower the power dissipation in the SRAM during standby or during read/write.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: December 21, 2004
    Assignee: International Business Machines Corporation
    Inventors: Fred John Towler, Robert C. Wong
  • Patent number: 6834334
    Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: December 21, 2004
    Assignee: International Business Machines Corporation
    Inventors: William D. Corti, Joseph O. Marsh, Michael Won
  • Patent number: 6829183
    Abstract: A semiconductor memory device having an active restore weak write test mode for resistive bitline contacts. During the write margin test a circuit is used to block the bitline restore devices from turning off during the SRAM write cycle.
    Type: Grant
    Filed: September 20, 2003
    Date of Patent: December 7, 2004
    Assignee: International Business Machines Corporation
    Inventor: George M. Braceras
  • Patent number: 6829682
    Abstract: A method for controlling the operation of a dynamic random access memory (DRAM) system, the DRAM system having a plurality of memory cells organized into rows and columns, is disclosed. In an exemplary embodiment of the invention, the method includes enabling a destructive read mode, the destructive read mode for destructively reading a bit of information stored within an addressed DRAM memory cell. The destructively read bit of information is temporarily stored into a temporary storage device. A delayed write back mode is enabled, the delayed write back mode for restoring the bit of information back to the addressed DRAM memory cell at a later time. The execution of the delayed write back mode is then scheduled, depending upon the availability of space within the temporary storage device.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: December 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Toshiaki Kirihata, Sang Hoo Dhong, Hwa-Joon Oh, Matthew Wordeman
  • Patent number: 6826113
    Abstract: A synchronous dynamic random access memory (SDRAM) semiconductor device which uses a command cancel function to improve reliability and speed of a memory system. The CC function takes advantage of the intrinsic delays associated with memory read operations at high clock frequencies, and the increased write latency commensurate with increased read latencies where non-zero latencies for read and write operations are the norm by permitting address and command ECC structures to operate in parallel with the address and command re-drive circuits. The CC function is extendable to future DDR2 and DDR3 operating requirements in which latency of higher frequency modes will increase due to a shift from 2 bit pre-fetch to 4 and 8 bit pre-fetch architecture.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: November 30, 2004
    Assignee: International Business Machines Corporation
    Inventors: Wayne F. Ellis, Mark W. Kellogg, Daniel J. Phipps