Abstract: A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.

Abstract: A method, a recording medium and an apparatus for testing a photomask are provided. In the disclosed method, a particular region of a photomask is selected, either from a physical instance of the photomask, or from the photomask as represented by a digital representation thereof. The particular region is then characterized by identifying a pattern type present in the particular region. A lithographic process stress condition is determined for the particular region, considering the pattern type, and thereafter, a result of lithographically patterning a feature is determined by simulating a photolithographic exposure, using the particular region of the photomask under the lithographic process stress condition. Then, it is decided whether the particular region of the photomask is acceptable based on the result of the simulated exposure only under the lithographic process stress condition.

Abstract: Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.

Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.

Abstract: To provide a dynamic semiconductor storage device featuring reduced power consumption and faster operation of a sense amplifier. The drain of a transistor N7 constituting an N-type sense amplifier NSAt is connected to a shared line SA, while the drain of a transistor N8 is connected to a shared line /SA. The drain of a transistor N9 constituting an N-type sense amplifier NSAb is connected to a shared line SA, while the drain of a transistor N10 is connected to a shared line /SA. The threshold voltages of transistors N7 to N10 range from 0.2V to 0.3V, which are lower than a threshold voltage of transistors P1 to P3. A supply voltage Vdd is applied to the gates of isolators BLIt and BLIb to clamp the supply voltage Vdd by the isolators BLIt and BLIb so as to set the internal voltage of an array to 0.8V, which is lower than the supply voltage Vdd by the threshold voltage of transistors N3 to N6.

Abstract: This invention teaches an apparatus and method for determining a more efficient quality assurance or reliability test screen without falsely rejecting, i.e., over stressing, short channel length devices during voltage stress test screening. Short channel lengths devices fabricated on a semiconductor wafer have a higher tendency to fail at voltage levels that would otherwise not harm long channel length devices. The failures, however, are not related to device defects. Protection to the more vulnerable devices is provided by determining the speed of the die prior to the voltage test screen, thus, segregating the devices based on operational speed performance. Next, a lower voltage is effectively applied during wafer probe test to the faster devices, which directly correspond to the population of short channel devices. A preferred measurement for device speed entails measuring the drain-to-source current of each FET, and dividing the resultant sum by the device gate channel width.

Abstract: A voltage supply bypass capacitor for use with a semiconductor integrated circuit chip or module comprising a ferroelectric dielectric having electromechanical properties designed to provide maximum losses at selected frequencies.

Abstract: A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.

Abstract: Defects in manufacturing of IC devices are analyzed by testing the devices for defects using results of LSSD technology to find at least one failing pattern that contains incorrect values. The failing latches are used as a starting point to trace back through combinational logic feeding the failing latches, until controllable latches are encountered. A decision is then made to continue the back tracing or not depending on whether the latter latches were clocked during the application of one of the failing patterns or not.

Abstract: A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.

Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.

Abstract: A Content Addressable Memory (CAM) cell with PFET passgate SRAM cells which results in a smaller cell size because of the more balanced number of 8 PFET devices and 8 NFET devices. The PFET passgates allow the size of the SRAM cell pulldown devices to be reduced, and lower the power dissipation in the SRAM during standby or during read/write.

Abstract: A method for controlling the operation of a dynamic random access memory (DRAM) system, the DRAM system having a plurality of memory cells organized into rows and columns, is disclosed. In an exemplary embodiment of the invention, the method includes enabling a destructive read mode, the destructive read mode for destructively reading a bit of information stored within an addressed DRAM memory cell. The destructively read bit of information is temporarily stored into a temporary storage device. A delayed write back mode is enabled, the delayed write back mode for restoring the bit of information back to the addressed DRAM memory cell at a later time. The execution of the delayed write back mode is then scheduled, depending upon the availability of space within the temporary storage device.

Abstract: A semiconductor memory device having an active restore weak write test mode for resistive bitline contacts. During the write margin test a circuit is used to block the bitline restore devices from turning off during the SRAM write cycle.

Abstract: A synchronous dynamic random access memory (SDRAM) semiconductor device which uses a command cancel function to improve reliability and speed of a memory system. The CC function takes advantage of the intrinsic delays associated with memory read operations at high clock frequencies, and the increased write latency commensurate with increased read latencies where non-zero latencies for read and write operations are the norm by permitting address and command ECC structures to operate in parallel with the address and command re-drive circuits. The CC function is extendable to future DDR2 and DDR3 operating requirements in which latency of higher frequency modes will increase due to a shift from 2 bit pre-fetch to 4 and 8 bit pre-fetch architecture.

Abstract: Method for forming a first one time, voltage programmable logic element in a semiconductor substrate of first conductivity type, forming a first layer beneath a surface of the substrate, the first layer having a second conductivity type. A trench is formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench.

Abstract: An apparatus for reading out multiple match hits from a content addressable memory (CAM), comprising a priority encoder for receiving a plurality of matchlines from a CAM and for encoding addresses of the CAM that are associated with the matchlines that indicate a match, and a matchline mask system for selectively masking off a matchline that indicates a match from the priority encoder after the address associated with that matchline is encoded by the priority encoder.

Abstract: A method of testing a circuit having multiple elements is disclosed. A plurality of faults representing the elements of the circuit for testing said circuit is created. The faults are grouped based on common attributes of the faults. A test pattern for each group of faults is created. Finally, the circuit is tested using test patterns for each group of faults.

Abstract: A semiconductor device having an increased intersection perimeter between edge regions of a first conductor and portions of a second conductor is disclosed. In one embodiment, the intersection perimeter is the region where the perimeter of a gate structure overlaps an active area. The intersection perimeter between the conductors directs the breakdown of the dielectric material, increasing the likelihood that the programming event will be successful. In at least one embodiment, the portion of a current path that travels through a highly doped area is increased while the portion that travels through a non-highly doped area is decreased. This decreases post-program resistance, leading to better response time for the device.

Abstract: A control circuit for a memory array device having one or more memory storage cells associated therewith includes a true bit-line and a complementary bit-line coupled to the one or more memory storage cells. A sense amplifier is coupled to the true and complementary bit-lines, the sense amplifier being configured to amplify a small voltage difference between the true bit-line and the complementary bit-line to a full level signal at predetermined high and low logic voltage levels. A bit-switch pair selectively couples the bit-lines and said sense amplifier to fan-in circuitry, and is further configured so as to couple the fan-in circuitry to the true and complementary bit-lines prior to the activation of a wordline associated with a selected cell for a write operation thereto. Thereby, the write operation to the selected cell is commenced prior to the completion of time associated with signal development on the true and complementary bit-lines.