Abstract: A method and system for testing wafers, and particularly a wafer test system employing probes to provide for electrical contact with a device under test (DUT) which is located on a wafer. More particularly, also provided is a method and system for implementing wafer tests where the probes first contact a simulated wafer which incorporates an array of spaced load cells to determine the optimum probe overdrive. The DUT is then tested at the optimum overdrive.

Abstract: A system having multiple encoders of different maximum error correction capability, which reduces the entire size of the system by allowing most of the system to be shared among these encoders. This is accomplished by using an encoder that is capable of calculating parities of 2 or more kinds of bit numbers with different error correction capability. The system includes a circuit that generates a modified word by assigning a predetermined value to input an information word; and a circuit that generates an intermediate signal “u” by a linear operation using a modified word and matrix “P”. These circuits are combined with linear operation circuits for generating value of parity p1, . . . , p&agr;, each of whose bit number is different, by a linear operation using all or part of the intermediate signal and matrixes Q1, . . . , Q&agr; respectively.

Abstract: A method for diagnosing defects in an integrated circuit comprising: providing a set of failing test patterns; for each failing test pattern in the set of test patterns determining if a single stuck-at fault could cause the failing test pattern and determining a node on which a defect causing the single stuck-at fault could reside; selecting those failing test patterns that could be caused by a single stuck-at fault; and for those selected failing test patterns determining a first set of sets of nodes, such that each of the selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from the first set of sets of nodes.

Abstract: A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.

Abstract: A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.

Abstract: An SRAM semniconductor memory device has an active restore weak write test mode for resistive bitline contacts. The weak write margin test a circuit is used to block the bitline restore devices from turning off during the SRAM write cycle. The weak write test mode of the SRAM array is preconditioned to a pre-determined data state during a standard SRAM write cycle. The full array address space is next written to the opposite data state with a signal write active signal. The write margin signal is then turned off and the contents of the array are read out. The cells that cannot be written during the weak write test are replaced with redundant cells, or the memory chip is discarded.

Abstract: A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.

Abstract: A method for testing the data strobe window (DQS) and data valid window (tDV) of a memory device (e.g., a DDR-type memory device) using the window strobe of a testing system.

Abstract: Deterministic random Logic Built In Self Test (LBIST) is disclosed that applies Deterministic Stored Pattern Tests (DSPTs) by using random LBIST. Basically, the present invention selects the appropriate pseudorandom pattern for use with a scan cycle that needs care bits. The scan cycle may be a current or future scan cycle. In particular, the present invention determines care bits for a particular scan cycle. A pseudorandom pattern is generated that is then aligned with the particular scan cycle. If the pseudorandom pattern contains the care bits, with the correct values and in the proper positions within the pattern, this alignment tests one or more logic devices.

Abstract: An input buffer for an optical receiver or transceiver which provides symmetrical hysteresis and zero static current, comprises two field effect transistors (FETs) which form the basic buffer logic circuit, two FETs which respectively provide offset voltages to the buffer logic FETs, and two FETs which provide positive feedback. In the preferred embodiment the input buffer provides multiple-channels, each channel comprising a component inverter designed to provide zero static current and symmetrical hysteresis for a different input signal mode.

Abstract: A match line circuit in a content addressable memory (CAM) has a match line coupled to a first pull-up device and a first pull-down device at a match node. The first pull-up device has selectively adjustable pull-up impedances associated with it. The match line circuit also includes a second pull-up device coupled to a second pull-down device at a float node, and an enabling signal for activating the match line circuit during a memory comparison operation. The enabling signal precharges the match node to a logic low level and the float node to a logic high level in between memory comparison operations.

Abstract: A localized direct sense architecture circuit includes a large number (e.g. 8) of microcells, each having a primary sense amp PSA, coupled to one global data line which is coupled to one secondary sense amp SSA. Each PSA includes its own bias current device, which supplies bias current to sense devices in the PSA and is also used for precharge, such that the bias current does not flow along the highly capacitive global data line. With this technical approach, the size of each bias current supply device can be substantially reduced, and the number of PSAs on one global data line can be increased for increased layout density.

Abstract: A test module having a lid to force a chip in contact with the test pads using a bed of nails to conform to the shape of the chip. The lengths of the nails are cut to conform to be of equal length above the chip with different size heads to apply the proper force. A pressurized bag may be placed above the head of nails to apply force to the chip.

Abstract: A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.

Abstract: A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell.

Abstract: An incremental fault dictionary in which the diagnostic simulation results of current tests are stored for future use. Diagnostic simulation results are incrementally added to the fault dictionary, and information in the incremental fault dictionary is used to avoid expensive redundant fault simulations. The size of the incremental fault dictionary is maintained within user definable bounds by identifying and deleting faults that need not be maintained in the incremental fault dictionary. The incremental fault dictionary beneficially provides more accurate and faster diagnostics than a typical prior art diagnostic fault simulation.

Abstract: A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell.

Abstract: In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

Abstract: Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.

Abstract: The present invention provides a method and apparatus that improves Built-In-Self-Test (BIST) flexibility without requiring the complexity of a compilable BIST circuit. Additionally, the present invention provides the ability to use a single BIST to test multiple memory arrays of different sizes. The preferred embodiment of the present invention provides a compilable address magnitude comparator to facilitate BIST testing of different size memory arrays without requiring customization of the BIST controller. The preferred embodiment compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller itself be compilable. In the preferred embodiment, the compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses that do not exist in the memory.