Abstract: An integrated circuit real-time data tracing apparatus for analyzing microprocessor based computer systems for monitoring, in real-time, parameters sufficient to define the load and store operations information that the embedded core controller may assert, and process information during events. Integral on this single chip apparatus is a data trace unit designed to access control, address, and data signal lines required to monitor the embedded core controller's activities; perform data tracing independent of instruction tracing; synchronize with an instruction trace stream; allow for selection of multiple ranges for data tracing; report lost events to a FIFO array; and, output strobe signals to give a cycle accurate indication of when an event has been captured.

Abstract: A solution is presented to keep track of the URLs that have been visited within an HTML file, identify the location or exit point of the last line that was displayed on a screen in a multi-screen HTML file, and return to the exact exit point location upon reentry to the web page by computing which section of the HTML file to display on the screen, and then displaying this section. The identification of whether a web page has changed after it has been visited by a user is also presented. A cyclic redundancy check is performed, comparing the current cyclic redundancy number with the last cyclic redundancy number obtained when the screen of exited multi-screen HTML file was last visited. If the web page has changed, the user has the option of viewing the web page at the top screen or going to the screen that contains the last exit position of the HTML file that was previously viewed.

Abstract: This invention teaches an apparatus and method for determining a more efficient quality assurance or reliability test screen without falsely rejecting, i.e., over stressing, short channel length devices during voltage stress test screening. Short channel lengths devices fabricated on a semiconductor wafer have a higher tendency to fail at voltage levels that would otherwise not harm long channel length devices. The failures, however, are not related to device defects. Protection to the more vulnerable devices is provided by determining the speed of the die prior to the voltage test screen, thus, segregating the devices based on operational speed performance. Next, a lower voltage is effectively applied during wafer probe test to the faster devices, which directly correspond to the population of short channel devices. A preferred measurement for device speed entails measuring the drain-to-source current of each FET, and dividing the resultant sum by the device gate channel width.

Abstract: A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.

Abstract: The amplification of target overlay errors of interleaved arrays in semiconductor fabrication is achieved by calculating the synthesized beat signal on a set of targets that are imaged using conventional microscopy and measured using a geometrical image processing algorithm. The interleaved arrays have differing periodicities resulting in a phase shift. The difference in periodicity distinguishes the arrays and amplifies the sensitivity to the overlay error. The phase-shift ensures that the elements of the arrays are interleaved and not overlapped. The beat signal has a zero crossing location that is proportional to the overlay error between the interleaved arrays, with a proportionality constant much greater than one. The overlay error is amplified by this proportionality constant. In an alternative embodiment, the geometrical image processing algorithm is first digitally filtered prior to obtaining the overlay error. This spatial filtering allows for noise suppression.

Abstract: In the present invention an electronic package assembly includes an integrated circuit positioned on a substrate. The substrate has substantially horizontal layers including horizontal signal wires having vertical thicknesses and resistance. In a preferred embodiment, first and second vertical thicknesses of the signal wires alternate from the top to the bottom of the substrate such that the signal wires with greater vertical thicknesses have lower resistance than the signal wires would typically have. A plurality of substantially vertical conductive vias traverse the horizontal layers such that the vertical conductive vias connect to the integrated circuit and connect with at least one of the horizontal signal wires. A circuit board positioned beneath the substrate includes connection members for connecting with, and terminating the vertical conductive vias.

Abstract: A method for a robotic semiconductor wafer processing system to correct for wafers that have become offset or off-center during wafer processing. This is accomplished by determining the amount of offset and re-centering the wafer during wafer transport to the next process station using a single station sensor to locate the wafer center point. Each single sensor located at each station activates when the wafer's edge traverses through the sensor's path. Directional coordinates for the measured designated points on the wafer's edge are calculated, and the intersection points of two circles, analytically derived from using the measured designated points as their centers, are determined. The intersection point closest to the true wafer center position represents the measured wafer's center point. This point is compared to the true wafer center position, and the wafer is then adjusted for this difference.

Abstract: The Multiple Discriminant Analysis system described provides three parameters: (1) a Dynamic Force Factor (DFF) that characterizes the dynamic forces which act to reduce operational life of the bearing; (2) a Bearing Degradation Factor (BDF) that characterizes the actual condition of the rolling element bearing; and (3) a Life Expectancy Factor (LEF) that characterizes the overall condition of the first two factors. Each factor is configured in scalar form, wherein readings range from acceptable, to caution/degradation, to action required. DFF combines low frequency and high frequency dynamic forcing function discriminants. BDF combines, in this case, four powerful diagnostic bearing fault process discriminants, in a formulaic composition. The composition accurately describes the actual rolling element bearing condition indicating optimum or warning of a potential failure condition. The normally voluminous vibration data is compressed into three easily understood, yet highly informative numbers.

Abstract: A mosaic or inlaid sputter target design suitable for conventional planar magnetron deposition, RF ionized physical vapor deposition, HCM ionized PVD, ionized metal plasma (IMP) deposition, or self-ionized plasma (SIP) deposition of multi-component alloys for use in integrated circuit metallization. Inlays are inserted within a planar sputter target in the shape of wedges, wires, or buttons to achieve uniform deposition of films on semiconductor substrates during sputtering. Metal alloy strips within a three-dimensional HCM target achieve the same uniform deposition. The deposition leads to the production of CuAl, CuBe, CuB, CuCd, CuCo, CuCr, CuIn, CuPd, CuSn, CuTa, CuTi, CuZr or CuZn alloy films deposited on the wafer. Non-copper films may also be deposited. The inlay-target adjoining surfaces may be machine stepped or tapered to limit wicking from the target backing material.

Abstract: An invention for monitoring user choices and selections on a search result web page and providing alternative query expressions to further narrow and enhance the user's search. Monitoring and recording user choices and selections is achieved by a query manager. Query strings are then standardized. The search is performed on an Internet search engine, and each search result item in the result output set is then associated with a list of alternative standardized queries by an alternate query matching manager. Each search result item in the result output set that is associated with the alternate queries is then flagged. The resulting flagged list of alternative queries is displayed to the user by a page presentation manager using a graphical user interface for subsequent user selection. Upon selection of the graphical user interface for alternate query expressions, an alternate query selection manager retrieves and displays each alternate query to the user.

Abstract: A method of testing a digital logic circuit comprises first providing a logic circuit having a plurality of interconnected circuits each having an input and an output; determining a gate level representation of the logic circuit including test nets for determining faults in the circuit; and identifying a portion of the nets which are most difficult to test, including nets which are most difficult to control and nets which are most difficult to observe. The method then includes inserting into the logic circuit control latches for nets which are determined to be most difficult to control and inserting into the logic circuit observation latches for nets which are determined to be most difficult to observe. Using the inserted control latches and observation latches, the method further includes testing the nets which are determined to be most difficult to control and nets which are hardest to observe and determining faults in the circuit.

Abstract: A method and apparatus for punching holes in a substrate which is disposed between a punch head with a fixed partial pattern of holes and a die having a full array pattern of holes. The punch head punches holes in the substrate by aligning with the die and contacting the substrate. Punches contained in the punch head articulate in at least one of x, y, and theta positions in order to precisely align with holes in the die thereby producing holes in the substrate which precisely match holes in the die.

Abstract: An apparatus and method for injecting gas within a plasma reactor and tailoring the distribution of an active species generated by the remote plasma source over the substrate or wafer. The distribution may be uniform, wafer-edge concentrated, or wafer-center concentrated. A contoured plate or profiler modifies the distribution. The profiler is an axially symmetric plate, having a narrow top end and a wider bottom end, shaped to redistribute the gas flow incident upon it. The method for tailoring the distribution of the active species over the substrate includes predetermining the profiler diameter and adjusting the profiler height over the substrate.

Abstract: An automated method of selecting differential pairs in an integrated circuit comprising loading the design database for the integrated circuit package, and selecting output parameters for the differential pairs comprises adjacency criteria for the different pairs, time of flight tolerances for the differential pairs, and the redistribution layers and their voltage references. The method then includes comparing the output parameters to the design in the design database, and obtaining a resulting differential pairs list. The differential pair list preferably includes differential signal pairs having electrical characteristics within a predetermined design tolerance range. At least some of the differential signal pairs may comprise individual wires or connectors not physically adjacent one another.

Abstract: A structure and method for connecting two levels of interconnect vertically spaced from each other by another level of interconnect by forming a first interconnect region to which contact is to be made, a first insulating layer over the interconnect region, and an etch-stop layer over the first insulating layer, and etching the etch stop layer to form an opening at a position over the first interconnect region. A second interconnect region is formed in contact with the first insulating layer and above the first interconnect region, a second insulating layer is formed over the first insulation layer and the etch stop layer, and an opening is formed in the second insulating layer overlapping the opening in the etch stop layer. The opening in the second insulating layer is extended through the first insulating layer and the openings in the first and second insulating layers are filled with a conductor to create a connection between the first interconnect region and a region above the second insulating layer.

Abstract: An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230° C. and detach from the electronic module during subsequent ref lows. A Pb—Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by means of a screening mask. Interconnect structures are then bonded to the I/O pad.

Abstract: Mask programmable conductors of the same construction as the mask layers they define are utilized for mask vintage identification. When the actual mask layer is altered, the change is recorded within the mask itself. Mask identification can be fabricated to identify the following type of mask layers: DT—deep trench; SS—surface strap; DIFF—Diffusion; NDIFF—N Diffusion; PDIFF—P Diffusion; WL—N wells; PC—polysilicon gates; BN—N diffusion Implant; BP—P diffusion Implant; C1—first contact; M1—first metal layer; C2—second contact; and, M2—second metal layer. Conducting paths that incorporate, in series, the mask programmable conductor technology devices are: M1-C1-PC-C1-DIFF-C1-M1-C2-M2; M1-C1-PDIFF-SS-DT-SS-PDIFF-C1-M1-C2-M2; M2-C2-M1-C1-PC-C1-M1; M2-C2-M1-C1-NDIFF-WL-NDIFF-C1-M1; and, M2-C2-M1-C1-NDIFF-C1-M1-C1-PC-C1-M1. These conducting paths are electrically opened with the omission of any of the layers in the series path.

Abstract: This invention provides an apparatus for injecting gas within a plasma reactor and tailoring the distribution of an active species generated by the remote plasma source over the substrate or wafer. The distribution may be made more or less uniform, wafer-edge concentrated, or wafer-center concentrated. A contoured plate or profiler is provided for modifying the distribution. The profiler is an axially symmetric plate, having a narrow top end and a wider bottom end, shaped to redistribute the gas flow incident upon it. The profiler is situated below an input port within the plasma reactor chamber and above the wafer. The method for tailoring the distribution of the active species over the substrate includes predetermining the profiler diameter and adjusting the profiler height over the substrate.

Abstract: Method for determining a more efficient quality assurance or reliability test screen without falsely rejecting, i.e., over stressing, short channel length devices during voltage stress test screening. Short channel lengths devices fabricated on a semiconductor wafer have a higher tendency to fail at voltage levels that would otherwise not harm long channel length devices. The failures, however, are not related to device defects. Protection to the more vulnerable devices is provided by determining the speed of the die prior to the voltage test screen, thus, segregating the devices based on operational speed performance. Next, a lower voltage is effetively applied during wafer probe test to the faster devices, which directly correspond to the population of short channel devices.

Abstract: An apparatus and method for controlling and optimizing a non-planar target shape of a sputtering magnetron system are employed to minimize the redeposition of the sputtered material and optimize target erosion. The methodology is based on the integration of sputtered material from each point of the target according to its solid angle view of the rest of the target. The prospective target's geometry is optimized by analytically comparing and evaluating the methodology's results of one target geometry against that of another geometry, or by simply altering the first geometry and recalculating and comparing the results of the first geometry against the altered geometry. The target geometries may be of many different shapes including trapezoidal, cylindrical, parabolic, and elliptical, depending upon the optimum process parameters desired.