Abstract: A multi-level shelf degas station relying on at least two heaters integrated within wafer holding shelves or slots, where the semiconductor wafers do not have direct contact with the heater shelves. The heaters provide conduction heating. In order to degas a wafer, the heater and wafer holder assembly is positioned in a sequential manner through each wafer slot to the next available slot. If a degassed wafer exists in the slot, a transfer chamber arm removes it. A loader arm then places a wafer in the available, empty slot and the stage is moved upwards to receive the wafer from the loader arm. The transfer chamber arm removes an individual wafer from the heater and wafer holder assembly allowing the removed wafer to be individually processed while the other wafers remain in the heater and wafer holder assembly. In some instances, a loader arm may also remove wafers.

Abstract: A system and method are described for separating the bulk connections for FETs on a semiconductor wafer from the supply rails, testing the wafer to determine if a shift in the threshold voltage, VT, of certain devices within the wafer, as defined by the bulk-wells, can remove an AC defect in the IC circuit, and tailoring the voltage or voltages applied to the bulk nodes, post-manufacture, such that the integrated circuit meets its performance targets or is sorted to a more valuable performance level. The method requires generating a gate level netlist of the IC's circuitry and performing timing calculations on these circuit netlists using static timing analyses, functional delay simulations, circuit activity analyses, and functional performance testing. The failures are then correlated to respective IC circuits, worst case slack circuits are investigated, and proposed changes to the threshold voltages are employed in the hardware.

Abstract: A precision punch and die device for punching holes in a ceramic substrate and method of assembling the device. The device comprises a punch which moves relative to a substrate for punching a hole in the substrate and a die assembly including one or more precision die plates and support plates for guiding a punch and punching a substrate.

Abstract: A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.

Abstract: An apparatus and method of forming an oxynitride insulating layer on a substrate performed by putting the substrate at a first temperature within the main chamber of a furnace, exposing the substrate to a nitrogen containing gas at a second temperature which is higher than the first temperature, and growing the oxynitride layer on the substrate within the main chamber in the presence of post-combusted gases. The higher temperature nitrogen containing gases are combusted in a chamber outside the main chamber. The higher temperature is in the range of 800 to 1200° C., and preferably 950° C. In a second embodiment, distributed N2O gas injectors within the main chamber deliver the nitrogen containing gas. The nitrogen containing gas is pre-heated outside the chamber. The nitrogen containing gas is then delivered to a gas manifold that splits the gas flow and directs the gas to a number of gas injectors, preferably two to four injectors within the main process tube.

Abstract: An apparatus and method for performing a Hedge Technique Analysis are used to enhance the performance of the functional logic design of a large scale integrated circuit while simplifying the underlying logic. The methodology first runs performance tests on the logic circuitry to assess the timing and characterize the logic paths; next, functional paths are identified and listed; common logic path leaves, twigs, and branches are then identified and ranked by the number of critical paths associated with each; all high ranking common logic path leaves, twigs, and branches are then collapsed; and, timing paths are re-run to characterize the final performance rating of the functional design.

Abstract: A high laser absorption copper fuse can minimize the laser energy needed to delete the fuse portion of the conductor. Significantly, this type of fuse structure would allow for formation of copper fuses that can be deleted with appreciably less incident energy, mainly by increasing the absorption of the fuse link at the given incident laser energies. A metal wiring line contains a fuse link segment wherein the fuse link segment is composed of a stack of at least two metals. The underlayer material in the stack of metals is the primary electrical copper conductor, and the overlayer metal, also an electrical conductor, primarily tungsten or titanium-tungsten in composition, has predetermined thickness and optical properties chosen such that the combination of the overlayer metal with the underlayer metal provides for high absorption characteristics to incident infrared energy.

Abstract: An apparatus and method of forming an oxynitride insulating layer on a substrate performed by putting the substrate at a first temperature within the main chamber of a furnace, exposing the substrate to a nitrogen containing gas at a second temperature which is higher than the first temperature, and growing the oxynitride layer on the substrate within the main chamber in the presence of post-combusted gases. The higher temperature nitrogen containing gases are combusted in a chamber outside the main chamber. The higher temperature is in the range of 800 to 1200° C., and preferably 950° C. In a second embodiment, distributed N2O gas injectors within the main chamber deliver the nitrogen containing gas. The nitrogen containing gas is pre-heated outside the chamber. The nitrogen containing gas is then delivered to a gas manifold that splits the gas flow and directs the gas to a number of gas injectors, preferably two to four injectors within the main process tube.

Abstract: A Defect Leakage Screen Test apparatus and method is introduced to eliminate or reduce steps in the failure analysis process of memory devices, such as DRAM cells, or to eliminate the necessity for the application of a physical failure analysis on the memory device. Special single bit failures due to leakage current, junction current, or threshold leakage current, are characterized by varying the p-well voltage of the memory device during the read operation of the test. The p-well voltage is varied with a test code Initial Program Load (IPL). Additional logic is provided on the memory IC to decode the IPL logic signals. In order to perform the p-well varying test, the memory device is provided with the following: IPL decoding logic; a reference voltage generator; an IPL voltage reference multiplexor; a p-well voltage feed-back circuit; and a differential amplifier circuit.

Abstract: Methods for forming metal interconnects are provided. An insulating layer is formed on top of a substrate and a via is formed in the insulating layer reaching to the substrate. The via then is filled with a sacrificial material and a trench aligned over the via is formed by removing an upper portion of the insulating layer and an upper portion of the sacrificial material within the trench. The sacrificial material preferably is selected to etch faster than the insulating layer. After forming the trench, remaining sacrificial material in the via is removed and the via and the trench are filled with a conductive material. In addition to a single insulating layer, the insulating layer on top of the substrate may comprise a first insulating layer formed on top of the substrate, an etch stop layer formed on top of the first insulating layer and a second insulating layer formed on top of the etch stop layer.

Abstract: An apparatus and method for injecting gas within a plasma reactor and tailoring the distribution of an active species generated by the remote plasma source over the substrate or wafer. The distribution may be uniform, wafer-edge concentrated, or wafer-center concentrated. A contoured plate or profiler modifies the distribution. The profiler is an axially symmetric plate, having a narrow top end and a wider bottom end, shaped to redistribute the gas flow incident upon it. The method for tailoring the distribution of the active species over the substrate includes predetermining the profiler diameter and adjusting the profiler height over the substrate.

Abstract: Solder compositions are introduced to interface between an IC chip and its associated heat exchanger cover. The solder compositions have a solidus-liquidus temperature range that encompasses the IC chip operational temperature range. The solder composition has the desired property of absorbing and rejecting heat energy by changing state or phase with each temperature rise and decline that result from temperature fluctuations associated with the thermal cycles of the integrated circuit chips. A path for high thermal conduction (low thermal resistance) from the IC chip to the heat exchanger to the ambient air is provided by an electronic module cover, configured as a cap with a heat exchanger formed or attached as a single construction, and made of the same material as the substrate, or made with materials of compatible thermal coefficients of expansion to mitigate the effects of vertical displacement during thermal cycling.

Abstract: Thermoelectric devices having enhanced thermal characteristics are fabricated using multilayer ceramic (MLC) technology methods. Aluminum nitride faceplates with embedded electrical connections provide the electrical series configuration for alternating dissimilar semiconducting materials. Embedded electrical connections are formed by vias and lines in the faceplate. A portion of the dissimilar materials are then melted within the tunnels to form a bond. Thermal conductivity of the faceplate is enhanced by adding electrically isolated vias to one surface, filled with high thermal conductivity metal paste. A low thermal conductivity material is also introduced between the two high thermal conductivity material faceplates.

Abstract: A compressible interposer comprising an interposer sheet having a plurality of apertures filled with a dielectric material having a substantially uniform suspension of conductive particles therein forming a plurality of conductive sites. Preferably, the number of conductive sites on the interposer are greater in number than the number of contact pads on the electronic components such that precise alignment of the interposer between the electronic components is not required. The apertures of the interposer sheet confine the conductive particles within the dielectric material such that during compression of the interposer between the electronic components, z-axis conductive pathways are formed without shorting in the x and y directions. Preferably, the interposer sheet comprises polyimide. Preferably, the dielectric material comprises polyimide-siloxane.

Abstract: Mask programmable conductors of the same construction as the mask layers they define are utilized for mask vintage identification. When the actual mask layer is altered, the change is recorded within the mask itself. Mask identification can be fabricated to identify the following type of mask layers: DT—deep trench; SS—surface strap; DIFF—Diffusion; NDIFF—N Diffusion; PDIFF—P Diffusion; WL—N wells; PC—polysilicon gates; BN—N diffusion Implant; BP—P diffusion Implant; C1—first contact; M1—first metal layer; C2—second contact; and, M2—second metal layer. Conducting paths that incorporate, in series, the mask programmable conductor technology devices are: M1-C1-PC-C1-DIFF-C1-M1-C2-M2; M1-C1-PDIFF-SS-DT-SS-PDIFF-C1-M1-C2-M2; M2-C2-M1-C1-PC-C1-M1; M2-C2-M1-C1-NDIFF-WL-NDIFF-C1-M1; and, M2-C2-M1-C1-NDIFF-C1-M1-C1-PC-C1-M1. These conducting paths are electrically opened with the omission of any of the layers in the series path.

Abstract: Thermoelectric devices having enhanced thermal characteristics are fabricated using multilayer ceramic (MLC) technology methods. Aluminum nitride faceplates with embedded electrical connections provide the electrical series configuration for alternating dissimilar semiconducting materials. Embedded electrical connections are formed by vias and lines in the faceplate. Methods for forming tunnels through lamination and etching are employed. A portion of the dissimilar materials are then melted within the tunnels to form a bond. Thermal conductivity of the faceplate is enhanced by adding electrically isolated vias to one surface, filled with high thermal conductivity metal paste. A low thermal conductivity material is also introduced between the two high thermal conductivity material faceplates. Alternating semiconducting materials are introduced within the varying thermal conductivity layers by punching vias within greensheets of predetermined thermal conductivity and filling with n-type and p-type paste.

Abstract: A respiratory device is disclosed that optimizes delivery of oxygen and detection of carbon dioxide to a user through the use of a flexible lever arm and mouthpiece which may be adjusted to deliver the oxygen toward the user's oral and nasal cavities, and detect carbon dioxide, exhaled by the user, from a separate orifice of the mouthpiece. The lever is supported by a rotatable adapter attached to a head mounted brace. The adapter can rotate through 180° for placement of the lever on either side of the user's head. The adapter is hinged to eliminate occluding and kinking during rotation. A hose having tubular members therein delivers the gases to and from the user. The hose traverses through the lever arm and adapter, terminating at the lever arm into the mouthpiece. The mouthpiece has a plurality of ports for fluid flow. The hose terminates at the other end in gas detection and delivery equipment. The hose may be segmented or one continuous piece.

Abstract: An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230° C. and detach from the electronic module during subsequent reflows. A Pb—Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by a screening mask. Interconnect structures are then bonded to the I/O pad.

Abstract: A measurement of thickness of a metal oxide layer on a solder ball connection during semiconductor fabrication is demonstrated by an in-situ capacitance measurement of the oxide layer. A linear relationship is shown between the reactance of the metal oxide and its thickness. This linearity is derived empirically, and correlated to Auger Spectroscopy test results for accuracy. The linear relationship demonstrated with these measurements exhibits a linear correlation coefficient, R2, greater than or equal to 0.974. This close, linear relationship allows for accurate testing of the oxide thickness using standard electrical parameter measurements during wafer fabrication.

Abstract: An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 mm thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer is comprised of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 mm for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.