Abstract: A circuit to encode image data. The circuit receives image data in four bit nibbles which are either all-zero nibbles or terminating nibbles containing at least one non-zero bit. The circuit output is a series of code words, each a multiple of four bits and up to twenty-four bits long, packed into eight bit output words. Each code word contains a first part containing a run length specifying the number of received all-zero nibbles and a second part specifying the bit pattern of the terminating nibble. The circuit uses PROMs for the look-up and control elements and a pipeline of registers to allow high speed operation.

Abstract: A plastic bite holder for securely holding a rigid cassette comprising a photoreceptor and a light proof cover for use as a dental x-ray imaging medium is described. The holder is molded into a single piece of polyethylene and has a tab onto which the patient bites, a backing plate and two gripping members for securely holding the cassette against the backing plate.

Abstract: A video signal white level corrector wherein a digital memory is used to store a correction signal which is applied to a signal multiplier to remove white level shading which results from optic and beam misalignment of a scanner. Video signals are applied to a multiplier 10, the output therefrom being the corrected video signal. The correction signal is stored for future use in a digital memory 14 after being compared to a reference voltage at comparator 20. In a first, or "store", mode, the output from the comparator 20 is coupled to an integrator 22, the output of which increases or decreases the gain of multiplier 10. In a second, or "operate", mode, the output from the digital memory is coupled to integrator 22 to also control the gain of multiplier 10.

Abstract: This invention is a plastic holder for holding a rigid photoreceptor in the mouth during the creation of dental bitewing and periapical x-ray images, and more particularly is a one-piece plastic holder comprising (1) a bitewing holder comprising a backing plate, a tab and two gripping members for holding the photoreceptor in secure contact with the backing plate, (2) a periapical holder comprising a backing plate and a gripping member for holding the photoreceptor in secure contact with the backing plate, and (3) a handle in the form of a plastic strip connecting the two holders.

Abstract: A pulsed high voltage variable duty cycle current generator is described. One embodiment comprises a constant current power supply cyclically driving either one or both halves of a transformer primary. The transformer primary is polarized so that there is a secondary current output pulse proportional to the value of primary current only when one half of the primary is driven. The secondary current is rectified, and the average dc secondary current valve is used to control the primary driver duty cycle so that the secondary average current is maintained at a predetermined level. Thus, the output is a series of current pulses where the output peak value is determined by the amount of constant primary current and the output average value is determined by the output duty cycle.

Abstract: An optical position encoder system comprising a circuit for removing the electrical bias usually associated with the optical sensor outputs, and for generating a voltage output varying with the encoder position to produce an indication of angular or linear displacement between zero crossings is described. In one portion of the circuit, sensor output signals 180 degrees out of phase are subtracted to automatically cancel the bias. In another portion of the circuit, signals 90 degrees out of phase are used to generate a voltage, the amplitude of which is a function of the grid position between grid zero crossings. To accomplish these results, two or more angularly displaced grids are required.

Abstract: A circuit for converting a digital signal from TTL to CMOS levels. The circuit delay is reduced by providing a transmission gate between the P and N type transistors in the first stage. This transmission gate has a high impedance during transistions and a low impedance during steady state conditions. In operation, for a rising input signal, the first stage transistors are isolated, allowing the first stage N type transistor to pull down the first stage output line without delay.

Abstract: A cleaning station for removing the residual toner from a dental x-ray sized photoreceptor plate after the image has been developed. The station comprises two sets of donor and foam cleaning rolls. The cleaning rolls are for removing toner particles from the plate, and the donor rolls are for transporting the cleaning liquid from a liquid delivery system to a nip between each donor and cleaning roll to create a standing wave of liquid at the nip and to flush away the toner particles.

Abstract: A predictor bit pattern comprising selected bits of the current and previous raster scan lines and a method of predicting a plurality of bits per clock are disclosed. Generally, a predictor is used prior to the encoding of data to increase the compression. The current bit in a bit stream is compared to the predicted value and a one is output when the two values are not equal. An efficient predictor will reduce the number of ones in a bit stream, which increases the zero run lengths and increases the efficiency of a run length encoding system. The described bit pattern contains bits close to the current bit to efficiently predict text data, bits distant from the current bit to efficiently predict halftone data, and ignores a plurality of intermediate bits to reduce hardware costs. A two step process is also described to allow a plurality of bits to be predicted in parallel.

Abstract: A predictor bit pattern comprising selected bits of the current and previous raster scan lines and a method of predicting a plurality of bits per clock are disposed. Generally, a predictor is used prior to the encoding of data to increase the compression. The current bit in a bit stream is compared to the predicted value and a one is output when the two values are not equal. An efficient predictor will reduce the number of ones in a bit stream, which increases the zero run lengths and increases the efficiency of a run length encoding system. The described bit pattern contains bits close to the current bit to efficiently predict text data, bits distant from the current bit to efficiently predict halftone data, and ignores a plurality of intermediate bits to reduce hardware costs. A two step process is also described to allow a plurality of bits to be predicted in parallel.

Abstract: A stepper motor controller circuit is described. The circuit comprises four power transistors configured to drive current in either direction through a stepper motor winding. A series resistor senses instantaneous current and a chopper is used to limit this current to some predetermined maximum value. Eight diodes protect the circuit against reverse, current surges, and a flip-flop guarantees a minimum duty cycle.

Abstract: In a reprographic system, a method for distinguishing halftone areas from text in an original. The system raster input scanner produces lines of binary data. A predetermined set of bits within a moveable window is inspected and the probability of that particular set of bits being taken from a halftone area of the original is assigned. The window is moved, bit by bit, and line by line, while an accumulation of probability scores is accomplished. Then, the determination, halftone or text, is made for each 32 by 32 bit block, based on a comparison of the accumulation to a predetermined threshold number. Finally, the block decisions themselves are inspected for halftone areas that may have been classified as text because of very high or low density. If surrounding blocks were determined to be halftone, the internal block will be corrected to halftone also.

Abstract: A raster input scanner (RIS) comprising a platen and light source, doubling mirror, lens and two CCD arrays for producing a bit stream output with twice the resolution produceable with a single CCD is disclosed. The doubling mirror is between the platen and lens, and produces two beams separated by a small angle. The lens focuses these beams as two lines at the image plane, where half of each intersects each CCD array. Glass plates, each intersecting and perpendicular to each beam, and rotatable about orthogonal axes, provide horizontal and vertical fine tuning.

Abstract: A circuit for stitching and balancing the outputs of two CCD arrays is described. The field of view of a high resolution CCD raster input scanner can be doubled by using a CCD array for each half of the scan. Then the CCD output analog pulses must be stitched together, the dc level equalized and restored to a common value, and the gains adjusted to match the video levels from the two CCD devices. The circuit described herein accomplishes these functions at high data rates and at low cost by stitching the video, eliminating the hold step produced by the sample-and-hold circuit, and adjusting the gains, all at the low voltage levels at which the CCD output signals were originally produced, before amplifying the resultant stitched video to a higher voltage level and converting to digital form.

Abstract: A circuit for compacting variable length data words into a fixed word length format is disclosed. Each variable length data word and its associated leading 0's are separated by a delimiter bit and stored in memory. When the memory is accessed, the output word is loaded in parallel into a first shift register and shifted to strip the leading 0's and delimiter bit. The remaining data bits are then shifted serially into a second shift register. When the second shift register is full, the resultant fixed length data word is latched out. When the first shift register is empty, the next word is loaded in from memory. In this way, a series of variable length words may be compacted into a series of fixed length words. This circuit is useful for compacting variable length Huffman codes since the boundaries between codes are self evident. This circuit can also be used as a character generator, where the variable length data output comprises the bits required to generate a character image on a raster scanned display.

Abstract: A circuit and method for decompressing video subsequent to its prior compression for transmission or storage. The circuit assumes that the original video generated by a raster input scanner was operated on by a two line one shot predictor, coded using run length encoding into code words of four, eight, or twelve bits and packed into sixteen bit data words. This described decompressor, then, unpacks the data by joining together the sixteen bit data words and then separately the individual code words, converts the code words into a number of all zero four bit nibbles and a terminating nibble containing one or more one bits which constitutes decoded data, inspects the actual video of the preceeding scan line and the previous video bits of the present line to produce depredictor bits and compares the decoded data and depredictor bits to produce the final actual video.

Abstract: This patent describes a user interface device (UI device) used for machine control. The UI device is comprised of a video display capable of presenting desired images to the machine operator and a touch sensitive device capable of detecting operator requests by means of the operator touching the surface of the video display. A standard keyboard may also be employed when typed responses are required of the operator or for infrequent use a QWERTY keyboard may be displayed on the Display. The UI device is controlled by a general purpose computer, which also controls the on-line machine. Visual elements presented to the user on the UI device's display include instructions in text (orthographic display), and images (imaginal display). Displayed images may include and log status indicators (E. g., meters, thermometers) and buttons which the operator can touch to signal control requests.

Abstract: A circuit to encode image data. The circuit receives image data in four bit nibbles which are either all-zero nibbles or terminating nibbles containing at least one non-zero bit. The circuit output is a series of code words, each a multiple of four bits and up to twenty-four bits long, packed into eight bit output words. Each code word contains a first part containing a run length specifying the number of received all-zero nibbles and a second part specifying the bit pattern of the terminating nibble. The circuit uses PROMs for the look-up and control elements and a pipeline of registers to allow high speed operation.

Abstract: A circuit for controlling the clock rate separately for each facet of a polygon used in a laser driven raster output scanner. The clock rate for facet #0 is servoed using a first order integrator (11) driven by a digital correction circuit which compares the actual number of pulses against the required number, and produces therefrom an analog correction pulse width which is applied to the integrator (11). A second order integrator (19) is used to compensate for leakage of charge from the parallel capacitor of the first order integrator (11), to improve performance. The remaining facets are then corrected for by assigning to each an individual correction voltage. This correction voltage is generated by counting clock pulses for each additional facet and using these pulse totals to generate individual analog correction voltages which are added to, or subtracted from the facet #0 voltage in an adder (18) which combines the facet #0 correction voltage with each individual voltage in sequence.

Abstract: An improved sample and hold circuit is disclosed. One field effect transistor (FET) is used as a switch between a variable input voltage connected to the source and a holding capacitor connected to the drain on the output line. The sampling pulse is applied to the gate, and is unavoidably coupled through the gate-to-drain capacitance to become a noise pulse on the output line. To cancel this pulse, a second compensating FET is provided. The sources and drains of these FETs are connected and the gate of the second FET receives a sampling pulse of opposite polarity. The second FET is biased off but the gate pulse is coupled through the source and drain capacitance to the first FET where it is used to cancel the original noise pulse on the output line.