Abstract: A circular high voltage field effect transistor suitable for inclusion in LSI circuits, and the process for making said transistor, are described. The transistor comprises a central drain and concentric circular field plate, gate and source. Alternate embodiments include an intermediate gate and resistive gate. Implantation and diffusion techniques are described for producing the source and channel regions, and various device dimensions may be varied to improve either current or voltage handling capability or speed capability.

Abstract: A reproduction scanning system having intermediate storage between input and output scanning stations wherein an input document is scanned in first and second directions, the first direction being orthogonal to said second direction, and the electrical signals representative of information on said scanned document being stored on an intermediate storage member for storage, signal processing or data manipulation. The information stored in the storage member may be read out and reproduced on a reproducing medium. Other system features include input scan reversal for alternate bound pages during bound volume scanning, synchronization of the system by a clock associated with the storage member, input/output interleaving with a print interrupt feature, image centering and edge fadeout for image reduction, and independent magnification demagnification by separately variable raster spacing.

Abstract: A circuit and method for the high speed generation and comparison of Hamming codes to enable the correction of an error burst is described. The circuit generates or compares n Hamming codes simultaneously with the data field transmission. Each code word is associated with a data field word comprising every n.sup.th bit. The resultant system corrects error bursts of up to n bits.Additional circuitry is included to enable the correction of error bits in parallel, increasing the system bandwidth.

Abstract: A method for rescreening a halftone image to produce an edge-enhanced halftone copy from a halftone original. The halftone original is scanned by a raster input scanner and the resultant analog voltage is compared to a reference voltage to produce a one bit per pixel bit stream, where a pixel is defined as the smallest image (picture) element discernable by the system. For example, in a raster input scanner using a CCD array, the smallest picture element, pixel, is the analog voltage output of one CCD cell. This voltage subsequently can be converted to a digital gray scale representation requiring a plurality of bits per pixel, or either analog or digital representation can be compared to an analog or digital reference voltage to produce a one bit pixel. A six bit per pixel gray scale output is produced therefrom by adding an integrated value and an edge enhancement value for each input pixel received.

Abstract: A circuit for converting a series of photoelectric element array voltage outputs into twice the number of binary bits is described. Each photodiode output voltage is compared against two reference voltages to produce a two bit code word signifying a low, medium or high photodiode output. This is then operated on by a circuit implementation of a logic equation to produce a two bit serial output. The result is the frequency doubling of a photodiode array output for greater fidelity during transmission and reproduction of the original image.

Abstract: A computerized controller for a sewing machine is described. A plurality of patterns is stored in the memory. These patterns may be sewn into the fabric as single patterns, as a group of patterns or as a continuing series of identical groups of patterns. The patterns themselves are also variable in position, size, length and height. The basis of this system is a micro-computer or micro-processor, for accessing stored pattern data for controlling the fabric and needle motion, for manipulating said pattern data and for output of said data to the sewing machine servo circuits in the predetermined order desired.

Abstract: A computer numerical control system for controlling a lathe or similar machine tool in the cutting of threads. One computer is used as an interpolator to produce speed commands in real time for producing a smooth cutting tool motion. A second computer is used as an axis controller for receiving said speed commands and for controlling the servo circuits of up to six machine tool axes. A resolver attached to the rotating spindle is utilized to synthesize a tachonometric signal, and is also connected to an interrupt circuit to measure the spindle speed and position. The interpolator then uses this spindle information to synchronize the cutting tool motion with the spindle angular speed and position to enable multiple passes of the cutting tool along the same thread line.

Abstract: A system for displaying to the pilot an indication to enable him to fly to a desired air speed and angle of attack, especially on takeoff. An artificial angle of attack error signal is generated from actual and desired air speeds and corrected by adding to it a differentiated pitch signal. The resultant calculated angle of attack error is displayed to the pilot unless flying to that indication would result in exceeding the actual maximum or minimum angle of attack limits, in which case an indication based on the actual exceeded limit is displayed.

Abstract: A cargo loading and unloading shutoff system is used to control transfer of loads between a cargo aircraft and a loading dock. Control logic means compares commands entered on a control console and the existing conditions in the aircraft and on the dock during a loading or unloading operation. On loading, the logic means shuts off the dock conveyor drive immediately when all loads are transferred to selected aircraft positions and then shuts off the aircraft conveyor drive a predetermined period later. On unloading, the logic means shuts off both the aircraft and dock conveyor drives simultaneously when all loads are transferred to selected dock positions. The logic means also prevents energization of the aircraft and dock conveyor drives when the number of load positions selected in the aircraft is different from the number of load positions selected on the dock.

Abstract: A vehicle guidance system including means for projecting a beam of light to guide a vehicle such as an aircraft on a glide slope, and means for pulse coding the upper the lower portions of the beam providing to the aircraft pilot an indication of the aircraft's position in relation to the glide slope. The upper and lower pulse coded portions of the beam are differentiated by color. Color coded pulses are also provided to differentiate this beam from other lights in the area of the runway.

Abstract: Apparatus for the automatic inspecting, programming and testing of programmable read-only memory (PROM) devices. Under computer control, this PROM Handling System will test a sequence of PROMs against new part specifications, program them in any sequence of bit patterns required by the next piece of machinery on the assembly line, mark the PROM with a four digit part number identifying the bit pattern contained therein, dry the ink in a heated chamber for a fixed amount of time, dynamically test each PROM bit for access time in a hot and cold environment, program and test replacement PROMs for the ones that had failed at any point in the process, sort the PROMs into the correct order as required by the next assembly line machine and output said tested and ordered parts into output sticks for manual delivery or automatically deliver them by a track arrangement to the next machine.

Abstract: A memory module containing addressable memory devices, and the circuits necessary to address and drive these devices, is configured so that a trade-off between memory size and word length can be made by rewiring the backplane. Thus, a single memory module design can be used for a variety of computer memory applications. This is accomplished by incorporating on the module a complete set of addressing and signal driving circuits, and allowing for the control of these module components through a system of control lines wired through the backplane.

Abstract: Circuits for the improved operation of microprogrammable computers are described. This improvement is accomplished by providing a set of read-only memory devices for storing the micro-code for all combinations of arithmetic logic unit function, carry bit and file register address than can be specified by an instruction word executed from Main Memory. In a universal microprogram designed to execute that family of Main Memory instructions that differ only in the functions specified above, the instruction word is used to address the read-only memory devices, the micro-code output of which is used to control the file, carry in bit and arithmetic logic unit. Through the use of these circuits a family of instructions may be executed by a single microprogram and at no increase in execution time over that required for the execution of a microprogram dedicated to a single instruction.

Abstract: A Read-Only Memory device in the CPU of a microprogrammable computer contains a diagnostic program suitable for self-testing the computer. A microprogram for loading this diagnostic program from the Read-Only Memory device into Main Memory is contained in the Control Memory of the CPU. When required, the diagnostic program is loaded into Main Memory and executed thus allowing for the testing of a computer without the need of operational peripherals.