Abstract: A method of manufacturing semiconductor components includes etching two trenches (105, 106, 805, 806, 1205, 1206) into a surface of a substrate (101, 801, 1201), lining the two trenches (105, 106, 805, 806, 1205, 1206) with an electrically insulative layer (107, 807, 1207) that is never completely removed from a first one of the two trenches (105, 106, 805, 806, 1205, 1206), and simultaneously filling the two trenches (105, 106, 805, 806, 1205, 1206) with a material wherein the material is never completely removed from the first one of the two trenches (105, 106, 805, 806, 1205, 1206) and wherein the second one of the two trenches (105, 106, 805, 806, 1205, 1206) becomes electrically coupled to the substrate (101, 801, 1201).

Abstract: The objective is to accurately determine the effective value of channel width in accordance with the design value of channel width when the channel width is scaled down, thereby accurately modeling the electrical characteristic of a MOSFET. An error &Dgr;W1 based on the length of the region extending from the field oxide film to the gate oxide film, an error &Dgr;W2 based on the “effect of stress” that occurs when the design value W of channel width is scaled down, and an error &Dgr;W3 based on the “effect of lithography” that occurs when the design value L of channel length is scaled down, are predetermined with respect to various values of W and L, and the effective value We of channel width is determined according to an equation: We=W−&Dgr;W1+&Dgr;W2+&Dgr;W3. The resulting effective value We is used to model the electrical characteristic of the device.

Abstract: A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.

Abstract: A semiconductor structure (10) having device isolation structures (43, 44) and shielding structures (39, 40). The shielding structures (39, 40) are formed in a semiconductor material (11) and the device isolation structures (43, 44) are formed within the corresponding shielding structures (39, 40). A noise generating device is formed within a first shielding structure (43) and a noise sensitive device is formed within a second shielding structure (44). The two shielding structures (39, 40) are grounded and prevent noise from the noise generating device from interfering with the noise sensitive device.

Abstract: An optical display system for magnifying the image of a liquid crystal display cell (314) used in a portable electronic device (310) such as a cellular phone or smart card reader having a light focusing and deflecting array (316), a light coupling element (318) and a magnifying lens element (110). The light focusing and deflecting array (316) includes an array of lenslets (410, 412, 414, 416, 418) that receive light rays from the liquid crystal display cell (314) and impart an angular component to the light rays. The magnitude of this angular component increases moving radially outward along the light focusing and deflecting array. The light coupling element (318) couples the deflected light rays to the magnifying lens element without substantial refraction thereof. The magnifying lens element (110) has a unitary lens having a biaxial gradient index of refraction, which causes the light rays to be bent initially outward then inward.

Abstract: A multi-level registration control system for a photolithography process includes a photolithography device that prints first, second and third layers on a wafer. A first overlay mark defines overlay errors in a first direction between the first and third layer. The first overlay mark also defines overlay errors between the second and third layers. An overlay measurement device measures the overlay errors and generates an overlay signal. A feedback controller is connected to the overlay measurement device and the photolithography device. The feedback controller receives the overlay error signal and generates and transmits an alignment correction signal to the photolithography device. The first overlay mark is a box-in-box overlay mark or a frame-in-frame overlay mark. By providing a single overlay mark to align three layers, the multi-layer overlay control system reduces scribe grid area and saves useful silicone surface area.

Abstract: A sensor device (20) comprises a sensor package (22) having a cavity (24) formed therein, a sensor die (26) mounted on a bottom surface (28) of the cavity (24) and a protective coating (30) formed over the sensor die in the cavity. The protective coating (30) is formed from a material, preferably a polymer material, which is arranged to have a graduated cross-linking density such that the material at the top of the cavity (24) has a high density of cross-linking and the material at the bottom of the cavity (24), which material is in contact with the sensor die, has a low density of cross-linking.

Abstract: A silicon carbide transistor (10) is formed from a silicon carbide film (14) that is formed on a silicon carbide substrate bulk (37). A conductor pattern layer (25) is formed on the silicon carbide film (14) and the silicon carbide film (14) removed from the silicon carbide substrate bulk (37) and attached to a substrate (11) of a dissimilar semiconductor material.

Abstract: A semiconductor die bonder (10) has a height adjuster (13) that is positioned next to the die bonding head (11). The height adjuster (13) assist in ensuring that die bonding head (11) positions a semiconductor die (36) at the desired bond line thickness.

Abstract: A semiconductor component comprises a substrate (101), a two flexible pressure sensor diaphragms (106, 303) supported by the substrate (101), and a fixed electrode (203) between the two diaphragms (106, 303). The two diaphragms (106, 303) and the fixed electrode (203) are electrodes of two differential capacitors. The substrate (101) has a hole (601) extending from one surface (107) of the substrate (101) to an opposite surface (108) of the substrate (101). The hole (601) is located underneath the two diaphragms (106, 303), and the hole (601) at the opposite surfaces (107, 108) of the substrate (101) is preferably larger than the hole (601) at an interior portion of the substrate (101).

Abstract: Method and apparatus for singulating semiconductor devices (21) is provided. This approach eliminates the need for an adhesive tape. A fixture (10) is provided to hold the joined semiconductor devices. The fixture has grooves (14 and 18) to accommodate a saw blade (35). The saw makes a cut in two directions thereby separating or singulating the semiconductor devices. Bars (24) are placed across the semiconductor devices when sawing in the second direction to hold the semiconductor devices in the holding fixture. A pick and place machine can then be used to remove the singulated semiconductor devices from the holding fixture.

Abstract: A semiconductor device (10) is formed in a semiconductor substrate (11) and an epitaxial layer (14). The semiconductor device includes a p-type body region (16), a source region (17), a channel region (19), and a drain region (34) formed in the epitaxial layer (14). A doped region (13) is formed in the semiconductor substrate (11) to reduce the drift resistance of the semiconductor device (10). The drain region (34) is formed from a plurality of doped regions (30-33) that can be formed with high energy implants.

Abstract: A lateral gate, vertical drift region transistor including a drain positioned on one surface of a substrate and a doped structure having a buried region therein positioned on the other surface of the substrate. The buried region defining a drift region in the doped structure extending vertically from the substrate and further defining a doped region in communication with the drift region and adjacent the surface of the doped structure. A source positioned on the doped structure in communication with the doped region and an implant region positioned in the doped region adjacent the surface and in communication with the source and buried region. An insulating layer positioned on the doped structure with a metal gate positioned on the insulating layer so as to define an inversion region in the implant region extending laterally adjacent the control terminal and communicating with the drift region and the source.

Abstract: A semiconductor wafer (11) having a dielectric layer (12) is used as a calibration standard (10) to calibrate thickness measuring equipment in a wafer processing or manufacturing area. The thickness of the dielectric layer (12) is maintained to a desired thickness by heating the calibration standard (10) to remove contaminants from the dielectric layer (12).

Abstract: A field effect transistor (30) has an array of transistors (31) made up of bonding pads (45-47) and sub-arrays of transistors (41-43). The bonding pads (45-47) are distributed between the sub-arrays of transistors (41-43) to reduce the maximum temperature that any portion of the FET (30) is exposed to while the FET (30) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion (101) of an array of transistors (95).

Abstract: An improved bipolar transistor (202) has an increased Early voltage and can be integrated on a semiconductor die with MOS transistors (201) and other types of devices to form an integrated circuit (200). A p-type base region (240) is disposed in an n-type collector region (252). An n-type emitter region (244) is disposed within the base region, and a p-type enhancement region (250) is formed to extend under the emitter region to a depth greater than the base depth. The improved bipolar transistor can be fabricated without significantly affecting the operation of other devices on the integrated circuit.

Abstract: A compact ROM array is formed in a single active region (5) bounnded by field oxide regions, the array being formed of one or more ROM banks (6, 7). Each ROM bank has a plurality of pairs of N+ bit lines (1-1 to 4-2), a plurality of conductive word lines (15-1 to 16-2) formed on top of, and perpendicular to, the bit lines, and left-select (11) and right-select (12-1, 12-2) lines arranged parallel to the word lines to enable particular transistor cells in the array to be selected to be read. The transistor cells (40, 41) are formed by adjacent portions of adjacent bit lines together with the portion of the word line extending between them. Isolation regions (43) between the transistor cells are formed by implanting the substrate between them with Boron dopant of a low energy and concentration after the bit and word lines have been fabricated and the transistor cells are programmed by implanting a channel region (42) with Boron of a higher energy and concentration after the low energy implantation step.

Abstract: A method of performing electron beam lithography on high resistivity substrates including forming semiconductor material on a high resistivity substrate and etching the semiconductor material to form mesas with electrically interconnecting bridges between the mesas. Semiconductor devices are formed in the mesas employing electron beam lithography and charges generated by the electron beam lithography are dispersed along the interconnecting bridges thereby preventing charge accumulation on the mesas. The bridges are removed by etching or sawing during die separation.

Abstract: An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently changed to define a drain region (24,33), a channel region (27,34), and a source region (30,35). The dopant concentration is modified during the formation of the channel region (27,34) to create a doping profile (50). The doping profile (50) has a first profile (51) that is constant and a second profile (52) that changes.

Abstract: A semiconductor device (10) is formed in a pedestal structure (16) overlying a semiconductor substrate (11). The semiconductor device (10) includes a base region (44) that contacts the corners (13) of the pedestal structure (16). Electrical connection to the base region (44) is provided by a conductive layer (28) that contacts the sides (12) and corners (13) of the pedestal structure (16).