Abstract: A selected bandgap reference (11) of a voltage generator (10) is operated at a duty cycle that is less than one hundred percent. The seclectable bandgap reference (11) has at a high current consumption when enabled and a low current consumption when disabled. The output voltage of the selectable bandgap reference (11) is stored on a storage element (13) when the selectable bandgap reference (11) is enabled. A high impedance amplifier (16) receives the stored voltage and generates the reference voltage.
Abstract: In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate.
Abstract: A leadframe for a semiconductor package is formed with an indentation on a bottom surface. A side of the indentation is used to form a mold-lock that assists in securing the leadframe to the encapsulation material of the semiconductor package.
Abstract: A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is disabled to minimize power dissipation. The two independently controlled currents are generated by a multiple output current high voltage device (12) responsively to two separate control signals (23,24).
Abstract: In one embodiment, a delay circuit is formed to use cascode coupled transistors to receive signals from a differential pair and increase the propagation through the delay circuit.
Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.
Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die.
Abstract: In one embodiment a bus hold circuit decouples an inverter of the bus hold circuit from an operating voltage responsively to an input receiving a signal having a voltage that is approximately equal to or greater than the value of the operating voltage.
Abstract: In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.
Abstract: In one embodiment, a voltage translator is configured to sense a change in a value of a supply voltage to the translator and responsively inhibit the translator from changing a state of the output of the translator.
Abstract: In one embodiment, a self-gated transistor includes a sensing portion that generates a sense signal that is used to drive the self-gated transistor.
Abstract: In one embodiment, conductors of a semiconductor device are routed to a contact platform of the semiconductor device by using electroless plating and screen-printing techniques.
Abstract: In one embodiment, a multiphase power control system uses two control lines from a PWM section to control the switch controllers of the system. The two control signals contain power control information in addition to timing information. The switch controller uses the two control signals to facilitate enabling and disabling a power switch of the multiphase power control system.
Abstract: In one embodiment, a pair of differential amplifiers have outputs coupled together. A signal received on one input results in signals coupled to the outputs that substantially cancel each other at the outputs.
Abstract: A receiver circuit (12) includes a first gate (24) that receives an input signal (VIN0, VIN1) and has an output (32, 34) for providing an output signal (VG0, VG1). A shifting circuit (20) is coupled for shifting the common mode potential of the input signal to produce a shifted signal (VSH0, VSH1). A second gate (22) has an input (27, 28) that receives the shifted signal and an output coupled to the output of the first gate.