Abstract: A sidewall-nitride isolation technology avoids stress-induced defects, while permitting a heavy channel stop implant to avoid turn-on of the field oxide transistor, by performing a two-step silicon etch. The first channel stop implant is performed after the first silicon etch, before the sidewall nitride is deposited. A further silicon etch is performed after the sidewall nitride is in place, and a second channel stop implant follows. The first implant can be a light dose, to avoid excess subthreshold leakage in the active devices due to field-assisted turn on at the corners of the moat regions, and the second implant can be a very heavy dose to provide complete isolation without any danger of the channel stop species encroaching on the active device regions.

Abstract: A two-port monolithic microwave amplifier, which uses a distributed negative resistance diode with gain (such as an IMPATT diode) as an active element. The diode is tapered (increasing in width but not in thickness) so that, as the RF signal propagates along the diode, it sees a wider and wider active diode region. This diode is operated in the power-saturated region, so that, as the RF signal propagates along the diode, terminal voltage remains essentially constant, but the RF current increases. This configuration is inherently undirectional.

Abstract: A monolithic amplifier having a common-gate input stage with a device transconductance which is higher than required for input match, and a load impedance presented to the common-gate stage which is not conjugate matched. The present invention teaches a common-gate configuration using an FET with higher transconductance and a higher output load impedance. Over narrower bandwidths, excellent input match is thus obtained with noise figures at least as good as those obtained with the common-source approach. This combination of noise figure and input match is achieved in a compact monolithic structure.

Abstract: In a distributed IMPATT structure, power is coupled out through a side contact. That is, in previously proposed distributed IMPATT structures the gain medium (the active region of the IMPATT) operates as a transmission line. The prior art has attempted to couple output power from the gain medium through an end contact, i.e. through a contact which intercepts the primary direction of energy propagation of the active medium. In the present invention, a side contact extends along the whole active region in a direction which is parallel to the principal direction of propagation of the energy in the active medium. Thus, the side contact plus the active region together can be considered as a single transmission line.The present invention can be configured as an oscillator, amplifier, phase shifter, or attenuator. When configured as an oscillator, multiple short active regions can be sequentially coupled to a single long microstrip, which serves as the side contact for each of the active regions.

Abstract: A quartz arsenic cell having a stabilizing valve used to generate hot arsenic vapor which is flowed into liquid gallium, to provide a melt of liquid gallium arsenide from which a crystal can be pulled. The stabilizing valve prevents negative relative pressure from occurring in the quartz arsenic cell, and thus prevents the molten material from being sucked back up into the quartz arsenic cell.

Abstract: Hydrogen annealing permits deposition of good quality polysilicon atop TiO.sub.2. Hydrogen annealing of TiO.sub.2 prevents the tremendous hydrogen affinity of as-deposited TiO.sub.2 from disrupting process reactions during deposition of polysilicon.

Abstract: The disclosure relates to a method for reducing impurity concentration in mercury cadmium telluride alloys wherein impurities are attracted to a region saturated with second phase tellurium during annealing in a saturated mercury atmosphere where the second phase tellurium and the impurities attracted thereto can be removed by polishing, etching, grinding, or the like.

Abstract: The disclosure relates to a method for removing the unwanted impurities from an HgCdTe alloy which consists of the steps of depositing a thin film on the order of from about 1 to about 100 microns in thickness of tellurium onto the backside of a mercury cadmium telluride bar to insure the presence of a substantial amount of excess tellurium on the backside of the alloy bar and allow the gettering mechanism to work. A protective film to shield the tellurium film from mercury ambient atmosphere is then optionally placed over the tellurium film. The protective film can be formed of a silicon oxide such as SiO and is preferably in the range of about 1000 angstroms to 10 microns or more in thickness. The bar with the tellurium and protective film thereon is then annealed at a temperature of less than 450.degree. C., preferably about 280.degree. C.

Abstract: A power-down inverter comprising three devices in series between supply voltage VDD and ground. A depletion load transistor connects the power supply rail to a first output node; a natural-threshold-voltage transistor, whose gate is controlled by the power-up signal, connects the first output node to a second output node, and an enhancement mode transistor, whose gate is controlled by the input signal to the inverter, connects the second output node to ground. This circuit provides an output (at the first output node) which is never floating, and it is therefore not necessary to use complementary signals for the power-up information. Moreover, the provision of two output nodes permits multiple output states to be available during the power-down mode if desired, depending on the full circuit configuration.

Abstract: In stacked CMOS, a single gate in first level polysilicon is used to address both an n-channel device in the substrate and an overlaid p-channel device. The p-channel polysilicon device has its channel self-aligned to the gate, by the use of a boron-doped oxide at the sidewalls of the gate. This boron-doped oxide provides a dopant source which dopes the second polysilicon layer to provide heavily doped source/drain extension regions which are self-aligned to the gate in first poly. A mask level is still required to pattern the sources and drains, but the self-aligned source/drain extension regions mean that the source/drain mask level can have a reasonable alignment tolerance.

Abstract: The disclosure relates to a method for making extrinsically doped HgCdTe alloys containing Cu, Ag, or Au or other dopant impurity whereby the excess tellurium in the core is annihilated (stoichiometrically compensated by excess in-diffusing Hg) and the dopant impurities are then permitted to randomly move through the slab to provide for homogeneity thereof. A post-annealing step of much greater than normal temperature-time length than was provided in the prior art is used. A standard post-annealing step in a saturated mercury vapor atomosphere leaves second phase tellurium (and gettered impurities) at the center of the slab, and longer term post-annealing negates this situation by annihilating the second phase tellurium in the slab and thus permitting the impurities to randomly travel by solid state diffusion throughout the slab to ultimately be distributed therein in a homogeneous manner.

Abstract: The access hole for filling the liquid crystal cavity in an LCD having plastic front and rear members is sealed by welding the two members together. Pressure is applied during the weld to insure a good joint. The welding process avoids problems of non-adhesion or poor adhesion associated with the use of epoxy, especially the type of epoxy used for sealing glass LCDs.

Abstract: The disclosure relates to a plasma etch chemistry which allows a near perfectly anisotropic etch of silicon. A Cl-containing compound such as HCl has HBr added thereto, readily allowing the anisotropic etching of silicon. This is due to the low volatility of SiBr.sub.4. The silicon surface facing the discharge is subjected to ion bombardment, allowing the volatilization (etching) of silicon as a Si-Cl-Br compound. The Br which adsorbs on the sidewalls of the etched silicon passivates them from the etching. This new plasma etch chemistry yields a very smooth etched surface, and the etch rate is relatively insensitive to the electrical conductivity of the silicon.

Abstract: A noninverting amplifier circuit for one propagation delay complex logic gates. The noninverting amplifier circuit is compatible with field effect transistor logic, including depletion-mode Schottky barrier field effect transistor (MESFET) inverting logic, gates. The basic noninverting amplifier circuit, utilizes field effect transistors (FET) and diodes, and comprises input interface means for receiving an input voltage signal, amplifier means for providing noninverted amplification of the input voltage signal, and buffer means for driving, and shifting the voltage level of the amplified input voltage signal. In another embodiment, additional circuit means for enabling performance of the "AND" logic function is included in the basic noninverting amplifier circuit. In a third embodiment, additional circuit means for enabling performance of the "OR" logic function is included in the basic noninverting amplifier circuit.

Abstract: A very simple oscillator circuit, using a FET pair with RF coupled, DC isolated gates, selectively operates at two widely separated microwave frequencies. The two FETs are DC isolated so that one of them can be pinched off (to act as a passive element) while the other remains active. Thus, for example, a two-FET push-push oscillator operating at 20 GHz can switch downband, when one FET is pinched off, to act as a fundamental mode oscillator at 121/2 GHz. The circuit is integrable. In alternative embodiments, more than two FETs are used, for switching over a wider frequency range when one or two of them is pinched off.

Abstract: The dielectric, which is provided on either side of the active phosphor in an AC-driven electroluminescent display, is formed of a composite material which has both high dielectric constant and high resistivity. Preferably, a composite of titanum dioxide and alumina is used.

Abstract: An improved MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a self-aligned gate process which consists of an implanted channel stopper underneath a thick field oxide, depletion and enhancement mode device channel implants, implanted source and drain regions, selective oxidation to form self-aligned gates, metal-semiconductor junctions as control elements, barrier metal and a thin film metallization system. The process and device structure are suited for high packing density, very low speed power product and ease of fabrication making it attractive for digital applications.

Abstract: The dislocation density near the surface of Hg.sub.1-x Cd.sub.x Te alloys is substantially reduced by annealing the material at around 600.degree. C. in a mercury saturated ambient for periods of four hours or more, prior to post annealing at lower temperatures to control the metal vacancy concentration. This procedure allows dislocation reduction by climb, reduces the concentration of metal vacancies which can collapse to form dislocation loops or contribute to dislocation multiplication, and reduces tellurium precipitates which contribute to dislocation multiplication during subsequent post annealing.

Abstract: A monolithic microwave voltage-controlled oscillator including one or more FETS integrated with a wide-ratio varactor. The varactor includes interdigitated anode and cathode patterns laid out on a single thin epitaxial layer. The punch through voltage of the epitaxial layer, and hence the resistivity-thickness product of the epitaxial layer, must be low. Since the substrate is semi-insulating, punch through to the substrate does not become uncontrollable, but simply permits modulation of the capacitance over a very wide range. The FETS are formed in the same epitaxial layer with the varactor, and complicated doping profiles are not required.

Abstract: In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anisotropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.