Abstract: A device for the erasure of sectors of a flash EPROM memory map comprises routing means to apply an erasing voltage to several sectors selected simultaneously by a predetermined resistor for all the sectors. Advantageously, the routing means enable the application of the erasing voltage to a sector selected individually by a resistor proper to the sector.

Abstract: A computer system having power management control features which include states of normal clock speed operation, slow clock speed operation, and stop-clock operation based on input/output activity, system bus activity, and program parameters. The system detects inactivity over a period of time and places the system in one of the states to provide for power conservation and accessibility by a user.

Abstract: Improvements are made in the movements of a gamma camera, especially a gamma camera provided with two detector heads, by supporting each of these detector heads with a stirrup provided with two flanks. A bearing can slide within each of the flanks. This bearing holds a pin for the angulation and holding of the detector head. Each detector head can thus be shifted in translation independently, when the two bearings shift together and in the same direction in the flanks. It can furthermore accept a movement of angulation when it is rotated on itself, even about these axes. It is shown that this device improves the ergonomy of use and that it furthermore enables better-quality imaging.

Abstract: A decision circuit receives input addresses of instructions to be executed and data addresses to which the instructions are to be applied. The decision circuit either allows the execution of the instruction or prohibits the execution of the instruction if the instruction leads to a false operation or to a fraudulent attempt to divulge the system contents. A buffer register stores the instruction addresses and subsequently presents them to the decision circuit simultaneously with the data addresses. This device applies particularly to the protection of electronic integrated circuit memory cards.

Abstract: A signal generator which includes two matched ring oscillators, and feedback gates which cross-couple each ring oscillator to the other. That is, in each oscillator, a first node gates a coupling transistor which connects a second node (complementary to the first node) across to drive the first node of the other oscillator.

Abstract: A dynamic reference system for a sense-amplifier is implemented by using an asymmetric pair of transistors (one twice the size of the other) in the current paths between two selected sensing lines and a source of a bias current in order to superimpose an offset current to the currents forced through the loads of the two sensing lines. The asymmetric transistors may be driven by the signals which are generated by a pair of cascode circuits which are normally used to drive the load-connecting switches of the sensing network or by the signals present on the "other one" of the two sensing lines. This introduces a dynamic behavior of the reference system during an evaluation phase of a reading cycle which follows a first capacitance-charging phase, thus enhancing overall discrimination performances of the sense amplifier. The reference system is simple to implement and offers a number of advantages as compared to "static" reference systems of the prior art.

Abstract: Regulator with small dropout voltage and high efficiency utilizes pass and free-wheeling field effect transistors having intercouplings to limit shoot through currents during switching.

Abstract: An electrically-programmable integrated circuit memory in which the selected memory cell is read by comparing its current output with that of a reference cell, plus a bias current. The bias current is different in test mode than it would be during a normal read operation. The result of this is that, in test mode, cells whose current output is marginal in the unprogrammed state will be detected as faulty, even though those same cells would correctly be read as unprogrammed.

Abstract: A circuit for the detection of current leaks on a bit line of a memory (such as an EPROM or flash EPROM), which includes a current generator and circuitry for applying zero volts to the gates of all the cells f the bit line. The detection information is delivered by a comparison circuit. It corresponds to the result of the comparison between the test current and the current flowing in the bit line. Advantageously, the detection circuit is incorporated into the read circuit of the memory. Also disclosed is an associated detection method, and a memory circuit which includes such a detection circuit.

Abstract: A decoder for a ROM matrix organized in selectable NAND parcels of cells utilizes four selection circuits driven through five buses for implementing a two-level decoding, thus driving less than all of the rows through a plurality of selectable drivers. The architecture of the row decoder, based on a subdivision into a plurality of row drivers renders the circuitry physically compatible with the geometrical constraints imposed by a particularly small pitch of the cells. Subdivision of row drivers has positive effects also on access time, reliability and overall performance of the memory as compared to a memory provided with a decoder of the prior art driving in parallel all the homonymous rows of all the selectable NAND parcels of cells.

Abstract: A CMOS circuit protected against latch-up. A limiter parallel to the internal circuitry of the CMOS circuit increases the external current for the triggering of the latch-up in the event of overvoltage on the supply. In one embodiment, the parallel limiter is intrinsically protected against electrostatic discharges. In another embodiment, the limiter is protected by a series connected resistor and a separate shunt-connected ESD protection structure.

Abstract: An electronic device structure which comprises a metal plate, a semiconductor material chip attached to the plate, terminal leads, interconnection wires between the leads and metallized regions of the chip, and a plastic body which encapsulates the whole with the exception of a surface of the plate and part of the leads. This structure has highly reliable means of electrical connection between at least one metallized region and the metal plate which comprise at least one metal beam resting onto the plate and being attached thereto by studs integral with the plate, and at least one wire welded between a metallized region of the chip and the metal beam between the studs. At least a portion of the beam and its connection wire are encapsulated within the plastics body.

Abstract: An integrated circuit bandgap voltage reference, in which the regulated voltage is equal to the sum of a first transistor's base-emitter voltage plus a voltage which is proportional to the difference between the base-emitter voltages of two transistors operating at different current densities, PLUS an additional voltage which is equal to the base-emitter drop of an additional transistor. The additional transistor is connected to an emitter resistor which ensures that variations in resistor values will cause the base-emitter drop of the additional transistor to vary oppositely to the base-emitter drop of the first transistor. The resulting voltage reference circuit has high stability and low power consumption.

Abstract: A transconductor differential stage for high-frequency filters, which has a MOS differential input pair with common sources. The drain of each MOS input is connected to the emitter of an npn bipolar. These two matched bipolars have their gates connected together with the gate of a third bipolar, which is diode-connected. Two matched current sources feed the two bipolars, and a third current source feeds the third bipolar. A single controlled current sink is connected to the sources of both MOS input transistors, and also (through a resistor) to the third bipolar.

Abstract: An integrated circuit memory which includes a subcircuit for generating a programmable reference voltages on-chip from an external high-voltage supply line. Depending on the mode of operation (test, read, write, etc.), the reference voltage is changed.

Abstract: A plurality of integrated circuit devices are bonded to a substrate. Signal traces for corresponding pins of the devices are run to the same location, but are not electrically connected. They are, however, located in close physical proximity at a designated location. At this designated location, a properly shaped and sized contact can be used to contact all of the corresponding traces simultaneously, allowing parallel burn-in of all devices on the substrate to be performed. The devices can still be tested individually after burn-in. Once functionality of the overall subsystem has been confirmed and encapsulation completed, a permanent contact can be made at the designated location to all traces simultaneously so that the devices will be in parallel, and the substrate can be encapsulated to form a completed subsystem.

Abstract: A novel double buffering subsystem, wherein a dual port memory is partitioned in software so that the top half of the memory is allocated to one processor, and the bottom half to the other. (This allocation is switched when both processors set respective flag bits indicating that they are ready to switch.) On accesses to this memory, additional bits tag the access as "physical," "logical," or "preview." A physical access is interpreted as a literal address within the full memory, and the double buffering is ignored. A logical access is supplemented by an additional address bit, determined by the double buffering switch state. A preview access is used for read access only, and goes to the opposite bank of memory from that which would be accessed in a logical access. This double-buffer architecture is advantageously used, in a multiprocessor system, at the interface between a numeric processor and a cache bus.

Abstract: A structure and method for forming contact vias in integrated circuits. An interconnect layer is formed on an underlying layer in an integrated circuit. A buffer region is then formed adjacent to the interconnect layer, followed by forming an insulating layer over the integrated circuit. Preferably, the insulating layer is made of a material which is selectively etchable over the material in the buffer region. A contact via is then formed through the insulating layer to expose a portion of the interconnect layer. During formation of the contact via, the buffer region acts as an etch stop and protects the underlying layer. The buffer region also ensures a reliable contact will be made in the event of an error in contact via placement.

Abstract: A bedding structure, including an innerspring mattress and a padded cover (enclosing the mattress) which provides added postural support (as well as extra thermal insulation and padding). The padded cover includes a sheet of convoluted foam which covers essentially the full length of the mattress. This sheet of convoluted foam is stiffened, over the middle part of the mattress length, by a complementary piece of convoluted foam which is mated with it. The increase in thickness caused by having two pieces of convoluted foam face-to-face is relatively small. Thus, this arrangement provides extra firmness under the torso, while maintaining an essentially flat upper surface. This cover structure can be retrofitted to existing innerspring mattresses.

Abstract: A substrate is provided as a test fixture for burning-in and testing integrated circuit devices. The substrate contains a plurality of unpackaged integrated circuit dice arranged in a regular matrix of rows and columns. The substrate is partitioned into an array of rectangles which can be easily broken apart. One integrated circuit die is attached in each rectangle. The integrated circuits are bonded to conductive traces in their respective rectangular areas, and the conductive traces are connected to common locations at one side of the substrate. Voltages can be applied to all of the devices simultaneously by contacting the common locations at the edge of the substrate. This allows for burn-in of all integrated circuit devices on the substrate in parallel, after which they can be separated and used individually on printed circuit boards.