Abstract: The invention relates to a digital signal processor in which two multiply accumulate operations are carried out in one machine cycle. Only one address generation unit is required for addressing two data words of both the X and Y memories, since in the main processing loop the least significant address bit is considered as "Don't care", so that an access operation to the memory results in two output data words at a time.

Abstract: In a Plug and Play environment different kinds of EEPROMs can be used having different access protocols without having to add an additional pin to the EEPROM to indicate its type. The first type of EEPROM has a code which indicates the first type stored on a predetermined address whereas the second type of EEPROM having a different read protocol has another code which indicates the second type stored on a consecutive address. When the Plug and Play controller accesses the EEPROM for a read either the code 1 or code 2 is outputted whereby the appropriate read protocol is identified.

Abstract: Electrically insulating but thermally conductive "heat shunt" components are attached to PC boards along with regular electronic components to improve heat dissipation. The heat shunts are typically a small bar of thermally conductive ceramic with spaced-apart metal mounting pads on the ends for soldering to the PC board. Their shape is similar to standard electronic components for placement by automatic machinery and they extend, for example, from a transistor collector contact pad on the PC board to an adjacent ground lead having holes plated through to the metal back plane of the PC board in contact with the heat sink.

Abstract: A planarized dielectric isolation region for semiconductor devices and integrated circuits is created by providing a semiconductor substrate, providing on the substrate an oxide/nitride mask with an opening for defining the isolation region and a closed portion for defining the desired semiconductor islands, anisotropically etching a trench into the semiconductor substrate, isotropically etching the substrate so as to slightly undercut the oxide/nitride mask, thermally oxidizing the substrate to form a thin oxide layer on the bottom and sidewall of the trench wherein the outer surface of the thermal oxide approximately lines up with the edge of the oxide/nitride mask at the top of the trench sidewall, filling the trench with a conformal deposited material (preferably a dielectric), providing a mask over the conformal material which is the complement to the trench etch or island mask but of smaller lateral dimensions so as to cover those portions of the conformal layer which do not rise up over the semiconduct