Patents Represented by Attorney, Agent or Law Firm Robert N. Rountree
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Patent number: 6480503Abstract: A circuit is designed with an encoder circuit (602) coupled to receive a data sequence. The encoder circuit produces a first encoded data sequence and a second encoded data sequence from the data sequence. A first spreading circuit (606) is coupled to receive the data sequence and the first encoded data sequence. The first spreading circuit produces a first modulated data sequence in response to a first code. A second spreading circuit (614) is coupled to receive the data sequence and the second encoded data sequence. The second spreading circuit produces a second modulated data sequence in response to a second code.Type: GrantFiled: March 1, 1999Date of Patent: November 12, 2002Assignee: Texas Instruments IncorporatedInventors: Hirohisa Yamaguchi, Mitsuhiko Yagyu
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Patent number: 6459722Abstract: A circuit is designed with a plurality of logic circuits (370-374) for producing an offset state matrix. The circuit includes a first logic circuit (380-383) coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit (390) is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix.Type: GrantFiled: December 4, 2000Date of Patent: October 1, 2002Assignee: Texas Instruments IncorporatedInventors: Sundararajan Sriram, Zhenguo Gu
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Patent number: 6449314Abstract: A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (rj(i+&tgr;j), i=0−N−1) during a first time (T0-T1) from an external source and coupled to receive a second plurality of signals (rj(i+&tgr;j), i=N−2N−1) during a second time (T1-T2) from the external source. The input circuit receives each of the first and second plurality of signals along respective first and second paths (j). The input circuit produces a first input signal (Rj1) and a second input signal (Rj2) from the respective first and second plurality of signals. A correction circuit is coupled to receive a first estimate signal (&agr;j1), a second estimate signal (&agr;j2) and the first and second input signals. The correction circuit produces a first symbol estimate ({tilde over (S)}1) in response to the first and second estimate signals and the first and second input signals.Type: GrantFiled: August 28, 2001Date of Patent: September 10, 2002Assignee: Texas Instruments IncorporatedInventors: Anand G. Dabak, Rohit Negi
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Patent number: 6424679Abstract: A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (rj(i+&tgr;j), i=0−N−1) during a first time (T0-T1) from an external source and coupled to receive a second plurality of signals (rj(i+&tgr;j), i=N−2N−1) during a second time (T1-T2) from the external source. The input circuit receives each of the first and second plurality of signals along respective first and second paths (j). The input circuit produces a first input signal (Rj1) and a second input signal (Rj2) from the respective first and second plurality of signals. A correction circuit is coupled to receive a first estimate signal (&agr;j1), a second estimate signal (&agr;j2) and the first and second input signals. The correction circuit produces a first symbol estimate (S1) in response to the first and second estimate signals and the first and second input signals.Type: GrantFiled: August 28, 2001Date of Patent: July 23, 2002Assignee: Texas Instruments IncorporatedInventors: Anand G. Dabak, Rohit Negi
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Patent number: 6424642Abstract: A circuit coupled to receive a sequence of signals is designed with a multiplication circuit (416, 420) coupled to receive a first signal, a second signal and a complex conjugate of the first signal. The second signal follows the first signal in time. The multiplication circuit produces a first product sequence of the first signal and the complex conjugate and a second product sequence of the second signal and the complex conjugate. A summation circuit (424, 426) is coupled to receive the first product sequence and the second product sequence. The summation circuit produces a first sum of the first product sequence and a second sum of the second product sequence.Type: GrantFiled: December 31, 1998Date of Patent: July 23, 2002Assignee: Texas Instruments IncorporatedInventors: Timothy M. Schmidl, Anand G. Dabak
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Patent number: 6404826Abstract: A circuit is designed with an estimate circuit (132) coupled to receive a plurality of predetermined signals (416-418) from an external source. Each of the predetermined signals is spaced apart in time. The estimate cit produces a first estimate signal in response to at least one of the plurality of predetermined signals. An averaging circuit is coupled to receive a data signal 420 and at least one of the plurality of predetermined signals. The averaging circuit produces an average signal from the data signal and at least one of the plurality of predetermined signals.Type: GrantFiled: December 22, 1998Date of Patent: June 11, 2002Assignee: Texas Instruments IncorporatedInventors: Timothy M. Schmidl, Anand G. Dabak, Srinath Hosur
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Patent number: 6400213Abstract: A circuit is designed with a first transistor (661) having a current path coupled between a supply terminal (32) and a first output terminal (665). A second transistor has a current path coupled between the first output terminal and a reference terminal. The current path of the second transistor current path has substantially the same width and length as the first transistor current path. A first comparator circuit (679, 685) has first (668) and second (23) input terminals and a second output terminal (681). The first input terminal is coupled to the first output terminal. The first comparator circuit produces a control signal in response to a voltage between the first and second input terminals. A generator circuit (80) receives the control signal and produces an output voltage at the supply terminal.Type: GrantFiled: March 2, 2001Date of Patent: June 4, 2002Assignee: Texas Instruments IncorporatedInventors: Albert Shih, Jeffrey E. Koelling
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Patent number: 6356605Abstract: A circuit is designed with a correction circuit (350) coupled to receive a first estimate signal (&agr;j1), a second estimate signal (&agr;j2), and a plurality of input signals from an external source along plural signal paths. The plurality of input signals includes a first and a second input signal (Rj1, Rj2) The correction circuit produces a first symbol estimate in response to the first and second estimate signals and the first and second input signals. The correction circuit produces a second symbol estimate in response to the first and second estimate signals and the first and second input signals. A combining circuit is coupled to receive a plurality of first symbol estimates including the first symbol estimate and a plurality of second symbol estimates including the second symbol estimate.Type: GrantFiled: November 19, 1998Date of Patent: March 12, 2002Assignee: Texas Instruments IncorporatedInventors: Srinath Hosur, Anand G. Dabak
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Patent number: 6345069Abstract: A circuit for detecting a signal is designed with a first serial circuit coupled to receive an input signal in response to a clock signal. The first serial circuit (121) has N taps (142-146) arranged to produce a respective plurality of first tap signals from the input signal (111). A first logic circuit (130, 132, 134, 148) is coupled to receive the plurality of first tap signals and one of N predetermined signals and the complement of N predetermined signals. The first logic circuit produces a first output signal (150) in response to the clock signal, the plurality of first tap signals and the one of N predetermined signals and the complement of N predetermined signals. A second serial circuit coupled to receive the first output signal. The second serial circuit has M taps (150, 172-184) arranged to produce a respective plurality of second tap signals from the first output signal, wherein a ratio of N/M is no greater than four.Type: GrantFiled: December 21, 1998Date of Patent: February 5, 2002Assignee: Texas Instruments IncorporatedInventors: Anand G. Dabak, Srinath Hosur, Sundararajan Sriram
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Patent number: 6331975Abstract: A communication circuit is designed with a processing circuit (11) coupled to receive a plurality of first control signals (40-45) and a second control signal (46) from a source external to the communication circuit during a predetermined time (49). The plurality of first control signals are equally spaced apart in time. The second control signal is proximate one of the first control signals (40). The processing circuit produces a power control signal in response to at least two of the plurality of first control signals. A serial circuit is coupled to receive the power control signal. The serial circuit produces the plurality of third control signals and the power control signal.Type: GrantFiled: October 28, 1998Date of Patent: December 18, 2001Assignee: Texas Instruments IncorporatedInventors: Srinath Hosur, Timothy M. Schmidl, Anand G. Dabak
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Patent number: 6329867Abstract: A circuit is designed with a delay circuit (300) coupled to receive a clock input signal (CLK) and a control signal (DFT). The control signal has a first logic state and a second logic state. The delay circuit produces a clock control signal (*CLK) at a first time in response to the first logic state and at a second time in response to the second logic state. A clock circuit (200) is coupled to receive the clock input signal and is enabled by the clock control signal. The clock circuit produces a first clock pulse signal having a predetermined width in response to a first transition of the clock input signal and produces a second clock pulse signal having the predetermined width in response to a second transition of the clock input signal.Type: GrantFiled: September 7, 1999Date of Patent: December 11, 2001Assignee: Texas Instruments IncorporatedInventors: Daniel B. Penney, William C. Waldrop, Jason M. Brown
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Patent number: 6297671Abstract: A circuit is designed with a first transistor (661) having a current path coupled between a supply terminal (32) and a first output terminal (665). A second transistor has a current path coupled between the first output terminal and a reference terminal. The current path of the second transistor current path has substantially the same width and length as the first transistor current path. A first comparator circuit (679, 685) has first (668) and second (23) input terminals and a second output terminal (681). The first input terminal is coupled to the first output terminal. The first comparator circuit produces a control signal in response to a voltage between the first and second input terminals. A generator circuit (80) receives the control signal and produces an output voltage at the supply terminal.Type: GrantFiled: August 26, 1999Date of Patent: October 2, 2001Assignee: Texas Instruments IncorporatedInventors: Albert Shih, Jeffrey E. Koelling
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Patent number: 6275084Abstract: A circuit is designed with a delay circuit (300,301,500) coupled to receive a bias (256) and a reference signal (242). The delay circuit produces a series of phase signals (214). The phase signals are spaced apart in time in response to the bias. Each phase signal has a respective time after the reference signal. Each phase corresponds to logic states of a plurality of data signals. An encoder circuit (900,1100) is coupled to receive a first phase signal and a first plurality of data signals (212). The encoder circuit produces a first encoded data signal (220) at a time corresponding to the respective time of the first phase signal. A decoder circuit (600,800) is coupled to receive a second phase signal and a second encoded data signal (220) corresponding to the respective time of the second phase signal. The decoder circuit produces a second plurality of data signals (212) corresponding to the second phase signal.Type: GrantFiled: June 10, 1999Date of Patent: August 14, 2001Assignee: Texas Instruments IncorporatedInventor: Hugh P. McAdams
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Patent number: 6268765Abstract: A circuit is designed with a first transconductor circuit (903) with a first input terminal (901) coupled to receive a voltage signal, a second input terminal (1017) coupled to receive a control signal and an output terminal. The first transconductor circuit has a gain responsive to the control signal. A first integrator circuit (905) has an input terminal coupled to the first transconductor circuit output terminal and has an output terminal. A second transconductor circuit (909) has an input terminal coupled to the first integrator circuit output terminal and an output terminal. A second integrator circuit (911) has an input terminal coupled to the second transconductor circuit output terminal and has an output terminal.Type: GrantFiled: December 15, 1998Date of Patent: July 31, 2001Assignee: Texas Instruments IncorporatedInventors: Venugopal Gopinathan, Maurice Tarsia, Davy H. Choi
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Patent number: 6266749Abstract: A circuit for measuring the access time of a memory circuit. The circuit includes a storage element 908 having an input terminal, an output terminal, and a clock terminal. The input terminal of the storage element is coupled to an output of the memory circuit 900. A clock signal source 906 is coupled to the clock terminal of the storage element and to a clock terminal of the memory circuit. The circuit also includes test circuitry 902 coupled to address and control terminals of the memory circuit and to the output terminal of the storage element. The test circuitry is operable to store or generate a test data pattern and compare the pattern to data output from the storage element. In one embodiment, the storage element is a data latch comprising a clock-enabled inverter serially coupled with a flip-flop. The flip-flop in one embodiment is a cross-coupled inverter storage cell or “keeper”.Type: GrantFiled: March 12, 1998Date of Patent: July 24, 2001Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, James N. Hall
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Patent number: 6240047Abstract: A memory circuit for operating synchronously with a system clock signal is designed with a memory array (250, 252, 254, 256) having a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits (502) produces a select signal at a respective column select line (108) in response to a first column address signal. A plurality of sense amplifier circuits (202) is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line (203). A control terminal of each select transistor of a group of sense amplifier circuits is connected to the respective column select line. A data sequence circuit (218) is coupled to receive four data bits from four respective data lines (210, 212, 214, 216) in response to a first cycle of the system clock signal.Type: GrantFiled: March 27, 2000Date of Patent: May 29, 2001Assignee: Texas Instruments IncorporatedInventors: Jeffrey E. Koelling, J. Patrick Kawamura
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Patent number: 6239650Abstract: A plurality of substrate bias circuits (14, 16, and 18) are designed to provide a stable substrate reference potential for a variety of operating modes. Only one of the bias circuits is enabled by a control circuit (12) at any time for any operational mode. An on-demand boost bias circuit (16) is enabled whenever a level detector (20) indicates substrate bias has exceeded a predetermined limit during special operating modes such as burn-in or parallel test.Type: GrantFiled: June 7, 1995Date of Patent: May 29, 2001Assignee: Texas Instruments IncorporatedInventors: Ching-Yuh Tsay, Hugh P. McAdams, Wah Kit Loh
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Patent number: 6230250Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is coupled to a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. Initial row and column addresses are latched into a row address buffer (48) and a column address buffer (49). The data are read out from the memory in an order corresponding to a control signal (WT) in synchronization with the system clock signal. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.Type: GrantFiled: December 6, 1999Date of Patent: May 8, 2001Assignee: Texas Instruments IncorporatedInventor: Wilbur Christian Vogley
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Patent number: 6223264Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is arranged with a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and a single select signal such as an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.Type: GrantFiled: June 17, 1994Date of Patent: April 24, 2001Assignee: Texas Instruments IncorporatedInventor: Wilbur Christian Vogley
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Patent number: 6219746Abstract: A synchronous memory (30), comprising a row address circuit (48,50) latches a row address signal in response to a system clock signal and a binary select signal. The row address circuit produces at least one row select signal. A column address circuit (49,51-54) latches an initial column address signal in response to the system clock signal and the binary select signal. The column address circuit produces a plurality of column select signals in synchronization with the system clock signal. A memory array (75) is arranged in rows and columns of memory cells. Each memory cell stores a respective data bit. The memory array simultaneously produces an integral multiple of M data bits in response to the row select signal and the plurality of column select signals. An output circuit (OMUX) is coupled to receive the system clock signal and the integral multiple of M data bits.Type: GrantFiled: December 6, 1999Date of Patent: April 17, 2001Assignee: Texas Instruments IncorporatedInventor: Wilbur Christian Vogley