Abstract: A system and method for providing privacy regions in a picture or video. In one example embodiment, a camera is provided which has a lens system and detector, image processing circuitry, compression and formatting circuitry, and control circuitry. Images or video taken from the camera are preferably corrected for distortion (such as that introduced by an anamorphic lens system) and sent to an operator's workstation, where a privacy region is defined. The privacy region is merged with the rest of the image, whether constant or dynamic, and displayed. Other processing, such as object tracking and alarms, can also be implemented at varying points in the process.

Abstract: A method and a system for tracking the motion of moving objects accurately on the entirety of a wide-angle video is disclosed. The method includes using a non-uniform scaling to selectively enhance pixel density, preferably in preparation for other image processing. In preferred embodiments, the further image processing (such as motion detection, object recognition, or tracking, etc.) functions better with the enhanced pixel density or distribution.

Abstract: A 3D graphics processing unit which performs rapid context switching from normal rendering tasks to isochronous tasks when required. Preferably a secondary rasterizer, having less capability than the primary rasterizer, is provided in hardware, so that the primary rasterizer does not have to be context-switched when isochronous tasks are started.

Abstract: A rotary drill bit includes a bit body that includes a plurality of upright legs that terminate in an exterior bearing surface. At least one roller cutter is affixed to a corresponding exterior bearing surface of one of the plurality of legs. The roller cutter has an exterior cutting surface and a base edge and defines an interior bearing surface that is complementary to a corresponding exterior bearing surface. At least one duct is defined by the lower surface of the lateral wall and is adjacent to at least one exterior bearing surface. A plug is disposed in the duct at a distance from the base edge one of the roller cutters so that if either the interior bearing surface or the exterior bearing surface wears beyond a threshold, the plug will cause a remotely-sensible indication of excessive bearing wear to be asserted.

Abstract: A drill string is equipped with a down hole sub assembly which contains sensors to detect equipment condition during drilling. The sub assembly has no electrical communication with the drill bit itself, and the sensors detect drill bit condition from vibrations or strain or other detectable phenomena. Sensors in the bit itself are not needed.

Abstract: An apparatus and method for monitoring and reporting downhole bit failure. Sensors are located on a sub assembly (which is separate from the drill bit itself but located above it on the drill string). Data from the sensors (preferably accelerometers) are collected in blocks, then analyzed in the frequency domain. The frequency domain is divided into multiple bands, and the signal power in each band is compared to that of another band to produce a ratio of powers. When a bit is operating at normal condition, most of the spectral energy of the bit vibration is found in the lowest frequency band. As a bearing starts to fail, it produces a greater level of vibration in the higher frequency bands. This change in ratios is used to determine probable bit failure. Bit failure can be indicated by a given ratio surpassing a given threshold, or by monitoring the standard deviation of the frequency ratios. When the standard deviation exceeds a certain value, a failure is indicated.

Abstract: In an integrated circuit, a diode is interposed between the semiconductor substrate and the contact pad to an external bias voltage, and the substrate is biased at an internal voltage reference. Between each contact pad of the integrated circuit and semiconductor substrate, there is positioned a protection device against permanent overloads and a protection device against electrostatic discharges. By isolating the semiconductor substrate from the external voltages source and by placing a protection device between each contact pad and the substrate, a broad, general protection of the integrated circuit is obtained against all the destructive phenomena such as overloads, positive and negative overvoltages, polarity reversal and electrostatic discharges.

Abstract: The present invention provides a structure and method for fabricating that structure which provides increased capacitance over the prior art while occupying a minimum of surface area of the integrated circuit. The present invention accomplishes this by interleaving multiple capacitor plates to provide increased capacitance while occupying the same surface area as a prior art capacitor providing a fraction of the capacitance provided by the present invention. The present invention is fabricated by providing a capacitor stack which includes interleaved plates of material which may be selectively etched and which is separated by appropriate dielectric material. One portion of the stack is masked while one set of the interleave plates is etched. The etched portion of the interleave plates is filled by a suitable dielectric and a contact is made to the remaining plates. A different portion of the stack is then exposed to an etch which etches the other set of interleave plates.

Abstract: Two-terminal active devices, such as IMPATT and Gunn diodes, are combined with passive devices in a monolithic form using a plated metal heat sink to support the active elements and a coated-on dielectric to support the passive elements. Impedance-matching circuitry is preferably placed very close to (or partially overlapping) the active device, thereby eliminating detrimental device-to-circuit transition losses.

Abstract: A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of the storage elements to a plurality of data lines. Protection circuitry is provided that is connected to the address lines for storing flags corresponding to selected groups of the storage elements to be protected. Write circuitry is provided that is connected to the address lines and to the array of storage elements for preventing the writing into the storage elements addressed by the address lines when the address is within the address of the protected groups. Control circuitry is provided that is connected to the protect circuit and the write circuit for controlling the input of the protect group addresses and for enabling the write circuit means during a write operation. The memory apparatus further includes the capability to provide protection from writing from a direct memory access source or from a central processing unit source.

Abstract: The disclosure relates to a method of passivating mercury cadmium telluride substrates wherein a substrate surface is lapped and cleaned and then placed in an electrolyte solution containing sulfide ions to electrolytically grow a sulfide passivating layer on the lapped and cleaned surface. A preferred electrolyte solution is formed with sodium sulfide, water and ethylene glycol.

Abstract: A memory for generating data signals responsive to a select signal, a means for generating an increment signal responsive to particular ones of the data signals, a counter for selectively outputting the select signal corresponding to a stored count value, and a means for selectively incrementing the stored count value in the counter responsive to the increment signal. In a preferred embodiment, the data processing system includes means for selectively generating first and second enable signals responsive to particular ones of the data signals and includes, a first counter for selectively generating a select signal corresponding to a stored count value responsive to the first enable signal and a second counter for selectively generating the select signal corresponding to a stored count value responsive to the second enable signal.

Abstract: Gates of individual devices on a slice are connected through a resistance to the device substrate, and through the same resistance to other device gates. This interconnection and high-resistance drain gives the gate protection from static charge buildup and subsequent catastrophic discharge which would result in a faulty device. This method protects each gate from the time of deposition to final device packaging.

Abstract: Isolation trenches are formed around selected areas on an integrated circuit device, and highly doped areas are formed in the epitaxial silicon surrounding such trenches. The device is then oxidized at a low temperature, and differential oxidation growth of the highly doped areas causes a thick field oxide to grow outside the trenches while only a thin oxide grows over the selected areas.

Abstract: The disclosure relates to a monolithic circuit and method of making same which includes the use of two substrates of different semiconductor materials or two substrates of the same semiconductor material wherein the processing steps required for certain parts of the circuit are incompatible with the processing steps required for other parts of the circuit.

Abstract: A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of storage elements to a plurality of data lines. Control circuitry is also provided that is connected to the array for regulating the reading and writing of data to and from the data lines to the storage elements addressed by the address lines. A pipeline circuit is also provided that is connected to the address lines and to array of storage elements to store in response to the control circuit an address contained on the address lines. This memory system architecture allows for the address to be stored to allow the second address to be placed on the address lines while the first addressed data is being accessed from the memory array. This memory system also provides for the parity to be generated for the data in the array during the access of the data for the first address or after the pipeline circuit has been loaded with the second address.

Abstract: A method and apparatus for testing VLSI processors using a bit-sliced bus-oriented data path include data and control monitors and BIT for the on-chip memory. The data monitor is used to compress output data produced by the data path. BIT implementation of a functional test coupled with the data monitor are used for an off-line self-test of the data path in field. The control monitor is used to decouple the testing task of the control section from that of the data path.

Abstract: The disclosure relates to a semiconductor substrate having an active area for formation of an IMPATT device which is formed as a plurality of separated fingers having a common n+ region to spread the area over which the IMPATT is disposed and which provides such additional area for dissipation of heat through the substrate.

Abstract: A linear spatial light modulator with two offset rows of pixels for slight overlap of images, and a printer system using such a spatial light modulator with dark field projection optics is disclosed. The pixels include electrostatically deflectable elements which all bend in the same direction to permit use of dark field projection. The addressing electrodes for the elements are beneath the reflecting surface and arranged perpendicular to the rows of pixels with half on each side of the rows. The printer uses a xerographic engine for conversion of modulated light into print, and an entire row is printed without any scanning.

Abstract: A test circuit, called a universal testing block (UTB) for on-chip testing of a VLSI subsystem such as a ROM or an ALU has several modes, including test generator and test evaluator, formed on the VLSI chip. The test generator circuit includes means for applying a predetermined test pattern to an input channel of the subsystem and may be a generator for generating pseudorandom test patterns for application to the subsystem. Alternatively, the test generator may be a counter which can be selectively activated to generate a binary up-count. The UTB also has a shift register mode having a serial input and output to enable serial data to be shifted into and out of the subsystem in parallel fashion. The test evaluator circuit receives output signals from the subsystem, and includes a parallel signature analyzer to generate a signature of the subsystem after the application of the test patterns by the input circuit to indicate whether the subsystem is fault-free.