Abstract: An apparatus and method for monitoring and reporting downhole bit failure. Sensors are located on a sub assembly (which is separate from the drill bit itself but located above it on the drill string). Data from the sensors (preferably accelerometers) are collected in blocks, then analyzed in the frequency domain. The frequency domain is divided into multiple bands, and the signal power in each band is compared to that of another band to produce a ratio of powers. When a bit is operating at normal condition, most of the spectral energy of the bit vibration is found in the lowest frequency band. As a bearing starts to fail, it produces a greater level of vibration in the higher frequency bands. This change in ratios is used to determine probable bit failure. Bit failure can be indicated by a given ratio surpassing a given threshold, or by monitoring the standard deviation of the frequency ratios. When the standard deviation exceeds a certain value, a failure is indicated.

Abstract: A computer system which includes at least one host CPU; at least two separate rasterizer units, interconnected to process at least some graphics rendering tasks jointly; and a shared graphics memory manager which sends requested data to both said rasterizers simultaneously.

Abstract: A graphics accelerator which includes a dedicated virtual memory manager which manages at least some host memory, as well as dedicated graphics memory, and which manages memory during mipmapping using at least two separate pools of memory.

Abstract: Systems, methods, and probe devices for electronic monitoring and characterization using absorbent media confined by a metallic mesh. The mesh allows a stream of liquid or gas to pass through the structure, so that the media will adsorb the material to which it is specific. This changes the permittivity of the media in which the electromagnetic field is propagating. This change in permittivity can be seen through the use of classical microwave methods such as phase shift, amplitude changes, frequency changes in a cavity or the frequency of an unbuffered oscillator. Some embodiments use a two cylinder structure, where an outer cylinder contains a material which selectively removes a chemical which may be in conflict with or would contaminate the sensing of the desired chemical. This outer cylinder does not play a part in the measurement because it is outside the metal shield which contains the measurement adsorbent, and is thus outside the electromagnetic field.

Abstract: Using inserts which are welded in place allows the use of hardfacing in the immediate vicinity of the inserts. Areas of high wear, such as cutting structures and gage areas, can use a combination of ultra-hard inserts with hardfacing for protection against wear. The inserts slows wear, while the hardfacing prevents erosion around the inserts.

Abstract: In an integrated circuit, a diode is interposed between the semiconductor substrate and the contact pad to an external bias voltage, and the substrate is biased at an internal voltage reference. Between each contact pad of the integrated circuit and semiconductor substrate, there is positioned a protection device against permanent overloads and a protection device against electrostatic discharges. By isolating the semiconductor substrate from the external voltages source and by placing a protection device between each contact pad and the substrate, a broad, general protection of the integrated circuit is obtained against all the destructive phenomena such as overloads, positive and negative overvoltages, polarity reversal and electrostatic discharges.

Abstract: The present invention provides a structure and method for fabricating that structure which provides increased capacitance over the prior art while occupying a minimum of surface area of the integrated circuit. The present invention accomplishes this by interleaving multiple capacitor plates to provide increased capacitance while occupying the same surface area as a prior art capacitor providing a fraction of the capacitance provided by the present invention. The present invention is fabricated by providing a capacitor stack which includes interleaved plates of material which may be selectively etched and which is separated by appropriate dielectric material. One portion of the stack is masked while one set of the interleave plates is etched. The etched portion of the interleave plates is filled by a suitable dielectric and a contact is made to the remaining plates. A different portion of the stack is then exposed to an etch which etches the other set of interleave plates.

Abstract: A microwave oscillator provides two outputs, of opposite phase, which are directly connected to provide the local oscillator inputs to a balanced mixer. Since no balun is used, very wide-band performance can be obtained.

Abstract: Two-terminal active devices, such as IMPATT and Gunn diodes, are combined with passive devices in a monolithic form using a plated metal heat sink to support the active elements and a coated-on dielectric to support the passive elements. Impedance-matching circuitry is preferably placed very close to (or partially overlapping) the active device, thereby eliminating detrimental device-to-circuit transition losses.

Abstract: A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of the storage elements to a plurality of data lines. Protection circuitry is provided that is connected to the address lines for storing flags corresponding to selected groups of the storage elements to be protected. Write circuitry is provided that is connected to the address lines and to the array of storage elements for preventing the writing into the storage elements addressed by the address lines when the address is within the address of the protected groups. Control circuitry is provided that is connected to the protect circuit and the write circuit for controlling the input of the protect group addresses and for enabling the write circuit means during a write operation. The memory apparatus further includes the capability to provide protection from writing from a direct memory access source or from a central processing unit source.

Abstract: The disclosure relates to a method of passivating mercury cadmium telluride substrates wherein a substrate surface is lapped and cleaned and then placed in an electrolyte solution containing sulfide ions to electrolytically grow a sulfide passivating layer on the lapped and cleaned surface. A preferred electrolyte solution is formed with sodium sulfide, water and ethylene glycol.

Abstract: A static random access memory wherein all cells have p-channel access transistors, p-channel driver transistors, and n-channel loads. The access transistors have a width to length ratio which is greater than the width to length ratio of the driver transistors.The bit lines are precharged close to VSS, and the wordlines are held near VCC in the off state. Thus the operating signals in the array of the SRAM of the present invention are opposite to those in SRAMs of the prior art.

Abstract: A memory for generating data signals responsive to a select signal, a means for generating an increment signal responsive to particular ones of the data signals, a counter for selectively outputting the select signal corresponding to a stored count value, and a means for selectively incrementing the stored count value in the counter responsive to the increment signal. In a preferred embodiment, the data processing system includes means for selectively generating first and second enable signals responsive to particular ones of the data signals and includes, a first counter for selectively generating a select signal corresponding to a stored count value responsive to the first enable signal and a second counter for selectively generating the select signal corresponding to a stored count value responsive to the second enable signal.

Abstract: Using the present invention, a gate for a MESFET may be fabricated having a minimum gate length while having a low resistance gate. In addition, the present invention provides a method for forming a gate and gate recess which are perfectly aligned which is the optimal structure for high frequency power MESFETs. A two layer masking layer is fabricated having a first layer which may be etched uniformly and a second layer of lithographic material which may be photolithographic material such as AZ resist. A gate opening is patterned in the photoresist material and a metal such as gold is deposited by evaporation from acute angles on opposite sides of the gate opening in the resist. The deposited metal serves as a mask which covers all but a very small portion of the opening in the photoresist. The silicon nitride layer is then etched to form a gate opening and gate recess.

Abstract: Gates of individual devices on a slice are connected through a resistance to the device substrate, and through the same resistance to other device gates. This interconnection and high-resistance drain gives the gate protection from static charge buildup and subsequent catastrophic discharge which would result in a faulty device. This method protects each gate from the time of deposition to final device packaging.

Abstract: Isolation trenches are formed around selected areas on an integrated circuit device, and highly doped areas are formed in the epitaxial silicon surrounding such trenches. The device is then oxidized at a low temperature, and differential oxidation growth of the highly doped areas causes a thick field oxide to grow outside the trenches while only a thin oxide grows over the selected areas.

Abstract: The disclosure relates to a semiconductor substrate having an active area for formation of an IMPATT device which is formed as a plurality of separated fingers having a common n+ region to spread the area over which the IMPATT is disposed and which provides such additional area for dissipation of heat through the substrate.

Abstract: A method and apparatus for testing VLSI processors using a bit-sliced bus-oriented data path include data and control monitors and BIT for the on-chip memory. The data monitor is used to compress output data produced by the data path. BIT implementation of a functional test coupled with the data monitor are used for an off-line self-test of the data path in field. The control monitor is used to decouple the testing task of the control section from that of the data path.

Abstract: A linear spatial light modulator with two offset rows of pixels for slight overlap of images, and a printer system using such a spatial light modulator with dark field projection optics is disclosed. The pixels include electrostatically deflectable elements which all bend in the same direction to permit use of dark field projection. The addressing electrodes for the elements are beneath the reflecting surface and arranged perpendicular to the rows of pixels with half on each side of the rows. The printer uses a xerographic engine for conversion of modulated light into print, and an entire row is printed without any scanning.

Abstract: A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of storage elements to a plurality of data lines. Control circuitry is also provided that is connected to the array for regulating the reading and writing of data to and from the data lines to the storage elements addressed by the address lines. A pipeline circuit is also provided that is connected to the address lines and to array of storage elements to store in response to the control circuit an address contained on the address lines. This memory system architecture allows for the address to be stored to allow the second address to be placed on the address lines while the first addressed data is being accessed from the memory array. This memory system also provides for the parity to be generated for the data in the array during the access of the data for the first address or after the pipeline circuit has been loaded with the second address.