Patents Represented by Attorney Robert P. Bell
  • Patent number: 6348917
    Abstract: A graphics subsystem includes hardware and/or software for permitting mip-maps to be dynamically switched based upon depth (Z) values. In addition, the system generates a SHIFT signal to permit automatic adjustment of texture parameters to facilitate retrieval of texture maps. The system includes a mip-map select logic or routine that compares the depth value of a pixel to be rendered with predetermined depth values. The depth values may be stored in a plurality of depth registers, and compared with the depth value of a pixel in a plurality of associated comparators. A mip-map is selected based upon the comparisons, and the SHIFT signal is generated to indicate the order of change with respect to a base reference mip-map. A texture engine receives the SHIFT signal and uses the associated base address of the selected mip-map and shifted texture parameters to define an address for the texture map.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: February 19, 2002
    Assignee: Cirrus Logic, INC
    Inventor: Gautam Vaswani
  • Patent number: 6334062
    Abstract: A portable radio telephone handset operates as a data transfer terminal as well as an analog cellular telephone subscriber station. Two modes of operation, an analog cellular communication mode and a Cellular Digital Packet Data (CDPD) mode, are available in the handset. The handset distinguishes between paging signals indicating CDPD mode communications and those indicating analog cellular communications. The handset also automatically preempts CDPD communications in favor of analog cellular communications such as those carried out in an AMPS configuration. The handset maintains an active status on a CDPD communication channel during a “sleep mode”, when the handset can carry out AMPS activity.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 25, 2001
    Assignee: Cirrus Logic, Inc.
    Inventor: Russell P. Cashman
  • Patent number: 6301296
    Abstract: A Digital Impairment Learning sequence which is designed for providing reliable estimate of digital impairments such as PAD, RBS, and CODEC type in the presence of analog impairments such as IMD, noise and changing line conditions. This estimate is used to derive optimum transmit symbol constellations for a modem connected digitally to a trunk so as to maximize its data transmission rate.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: October 9, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Vedavalli Gomatam Krishnan, Jeffrey Allan Green, Xuefeng Jiang
  • Patent number: 6285536
    Abstract: A high voltage input pad and method for accepting electrostatic discharge (ESD) surges without damage to an input semiconductor amplifier. The protection system includes a metal gate, transistor, and n-well resistors which provide ESD protection. Protection is further provided against large voltages coupled to an amplifier by connecting an input bipolar junction transistor to the negative input connection of the amplifier. Negative surges are directed to ground with an anode grounded diode connected at its cathode to the negative input connection of the amplifier.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: September 4, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Douglas R. Holberg, Nadi R. Itani, David R. Welland
  • Patent number: 6266753
    Abstract: A virtual memory manager for a multi-media engine allows individual media units to operate in their own virtual space in much the same way as a software program operating in virtual mode. The virtual memory controller performs address translation or mapping to the correct physical memory location (in local memory or system memory) and will also convert the data stream to or from a compressed format. In addition, the virtual memory controller provides a unified TLB (translation lookaside buffer) available to all media units. The TLB has four types of pointer entries which are controlled by two bits. The first bit controls whether the TLB entry is a direct map or a pointer to another translation table. the second bit controls whether the TLB entry is stored in a compressed format. The overall concept may allow dynamic load balancing between local media memory and system memory.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: July 24, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Gary D. Hicok, Jeffery M. Michelsen
  • Patent number: 6260177
    Abstract: A method and system to use a standard cell function library to automatically configure gate array cells in an integrated circuit layout is provided. A standard cell netlist at the transistor level is compiled to list the transistors required in implementing the desired functions. Based on the netlist, gate array cells are restructured so that they can be inserted in locations designed for standard cells. The restructured gate array cells, which are made up of single poly and double poly structures, are strategically placed in a layout. Using the function net connectivity patterns from the standard cell function library, the gate array cells are connected to implement desired logic functions.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: July 10, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Kuochun Lee, Ying Cui, Tsung Yen Chen
  • Patent number: 6256549
    Abstract: The present invention provides a computerized database comprising a first table representing a list of part numbers. The database provides computerized links between individual part numbers and associated manufacturing process data for different process steps for that part number. Rather than correlate data by hand, a user may click on a process step for a particular part number to instantly and accurately retrieve that data. Manufacturing process data may include, for example, backgrind process data, wire binding data, either in numerical or graphical form, testing parameters, packaging data, and labeling data. The database system of the present invention may be used to automatically program various process equipment in an assembly facility with appropriate process data to automatically process finished semiconductor wafers into packaged semiconductor circuits.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: July 3, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Bernadette P. Romero, Carl H. Fong
  • Patent number: 6252606
    Abstract: A graphics processor capable of rendering three-dimensional polygons with color, shading; and other visual effects also corrects interpolation errors that occur as a result of mapping the polygon to a pixel grid display. The processor renders polygons using an Incremental Line-Drawing algorithm and features an error correction circuit capable of adjusting the initial and incremental gradient parameters for each pixel characteristic and then rendering each scan line with the proper orthogonal adjustment. The error correction circuit includes an ortho correction engine for correcting errors in the initial and incremental pixel parameters and an ortho adjust engine to accommodate overflows in the x-coordinate calculations. The processor is able to render the polygons with monotonic gradients in color, shading, depth, and other visual characteristics without interpolation error.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: June 26, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Gautam Vaswani, Daniel P. Wilde, Patrick Harkin
  • Patent number: 6241612
    Abstract: Real-time synchronized voice communications during a multi-player game is disclosed. A server is connected to client computers, players. Players can speak into a microphone and have their voice transmitted to all players or a select few. Digitized voice communications are transmitted along with other game data. Player speech and game data is synchronized and reproduced in the same order it was captured.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: June 5, 2001
    Assignee: Cirrus Logic, Inc.
    Inventor: Rafael Heredia
  • Patent number: 6219040
    Abstract: The present invention allows a single display controller design to be used in multiple markets by providing an additional stand-alone circuit which converts conventional analog CRT display signals to digital flat panel display or other digital display signals. A single VGA CRT controller may be implemented in both desktop and portable (e.g., laptop) markets thereby reducing the cost of the display controller through the economies of scale. For a laptop or other digital display markets, the apparatus of the present invention may be applied to a conventional analog CRT controller to convert analog CRT signals to digital laptop signals to generate a display on a flat panel display or other digital device. In addition, the apparatus of the present invention may be incorporated into a stand-alone flat panel display intended for use as a replacement for conventional CRT monitors. The apparatus of the present invention accepts a conventional analog CRT input and outputs digital flat panel display signals.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: April 17, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Sridhar Kotha, Rakish K. Blindish
  • Patent number: 6182965
    Abstract: A plurality of circular disks or rings, each disk or ring having a different color, number or other indicia affixed, printed or otherwise incorporated onto each of its two flat sides may be spun by hand to fall with one or the other of their two flat sides facing upward and showing the color, number or other indicia from which to determine score or playing action. Indicia on the disks or rings may be linked to other indicia, such as that on playing cards, game boards, pawns and the like, providing increased game complication. As an educational game, such linking of the ring indicia with external indicia may provide pre-game opportunities to select the level of difficulty. A plurality of such two-sided rings may provide combinations of the ring indicia, such as color combinations, and these combinations themselves may bring into play external indicia or may denote other playing action.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: February 6, 2001
    Inventors: Charles R. Escott, Esther R. Escott
  • Patent number: 6181347
    Abstract: A graphics system including a selectable mode smoothing filter for improved texture mapping. An x, y pixel coordinate is mapped into a u, v texture map. The mapped u, v coordinate includes integer and fractional portions. Depending on the location of the coordinate relative to the four nearest texels, which are represented as integers, one of several texture mapping schemes are used to either select or calculate the texel value to be used to render the pixel at the x, y screen location. The three texture mapping schemes include point sampling in which the nearest texel from the texture map is selected, two-texel averaging in which the closest two texels are combined in a weighted average, and four-texel averaging in which the closest four texels are combined in a weighted average. Scale factors in the range of 0 to 1 are computed for averaging texel values together.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: January 30, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Goran Devic, Christopher Shaw
  • Patent number: 6157386
    Abstract: A graphics system includes a graphics controller for rendering polygons with texture using an improved MIP mapping technique in which texels from multiple MIP maps are blended together. The graphics controller includes a polygon engine for rendering the pixels in a polygon and at texture map engine for selecting texture elements ("texels") from an appropriate texture map to be applied to the pixels rendered by the polygon engine. The texture map engine generates texel coordinate values from pixel coordinate values provided by the polygon engine. Texel values are selected from a set of texture maps each map varying from the others by the level of detail of the texture in each map. The graphics controller computes a scale factor for each texel value according an are a bounded by adjacent texel coordinates generated by the texture map engine. The scale factor is then used to compute a weighted average of texels form more than one MIP maps.
    Type: Grant
    Filed: October 10, 1997
    Date of Patent: December 5, 2000
    Assignee: Cirrus Logic, INC
    Inventor: Daniel P. Wilde
  • Patent number: 6149285
    Abstract: An elongated thin wall plastic tube device, containing decorative un-printed images along its length as transparent light-transmissive openings, while also containing printed or painted opaque sections to block out unwanted light-transmission around the images. The decorative tube device will surround a fluorescent light bulb color sleeve, which in combination with a fluorescent light bulb are inserted into a fluorescent lighting fixture. Once the fixture is powered on, the light transmitted by the light bulb passes through the color sleeve and through the un-printed image openings, while the opaque sections block out unwanted light around the images and throughout the remaining sections of the decorative tube device. When illuminated, the apparatus give the appearance of neon signage at a fraction of the cost of conventional neon signs.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: November 21, 2000
    Inventor: Gus M. J. Cicarelli
  • Patent number: 6142746
    Abstract: A pump device is disclosed, comprising a supply tube 1, for a liquid with a relatively low head, an accumulator 3 connected to supply tube 1 via a one-way valve 2, an outlet tube 4 from the accumulator for liquid with a relatively high head, and an outlet valve, provided at the supply tube 1 after the accumulator, which outlet valve opens and shuts an outlet 5 at the supply tube 1. The pump device is primarily characterized in that the outlet valve comprises a damper 6 movable between a position, in which the opening 5 is left open, and a position, in which the opening 5 is closed.
    Type: Grant
    Filed: April 23, 1999
    Date of Patent: November 7, 2000
    Inventor: Lars-Olof Lundgren
  • Patent number: 6139124
    Abstract: A stand comprises at least one substantially vertical first portion, carrying at least one first guide, provided to guide the slider between a rear stable first position for a load like a box or basket, and a front second position from which the load can be released from the slider relatively easily, the first guide being designed longitudinally, extending from the rear portion of the stand from a relatively low point, to the front portion of the stand at a relatively high point.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: October 31, 2000
    Inventor: Bengt Erik Hoger Kling
  • Patent number: 6130674
    Abstract: A graphics system including a selectable mode filter for improved texture mapping. An x, y pixel coordinate is mapped into a u, v texture map. The mapped u, v coordinate includes integer and fractional portions. Depending on the location of the coordinate relative to the four nearest texels, which are represented as integers, one of several texture mapping schemes are used to either select or calculate the texel value to be used to render the pixel at the x, y screen location. The three texture mapping schemes include point sampling in which the nearest texel from the texture map is selected, two-texel averaging in which the closest two texels are combined in a weighted average, and four-texel averaging in which the closest four texels are combined in a weighted average. By providing a selectable filter than can perform point sampling or two or four-texel averaging, the speed benefit of point sampling can be approached as well as the superior quality of two and four-texel averaging.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: October 10, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Gautam P. Vaswani, Daniel P. Wilde, Thomas Anthony Dye
  • Patent number: 6118413
    Abstract: A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: September 12, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Vlad Bril, Rakesh Bindlish, Ken Fuiks, Robin Sungsoo Han, Sridhar Kotha, Alexander Julian Eglit
  • Patent number: 6111420
    Abstract: The apparatus of the present invention includes a frame for attaching the clamp of a hand test socket to a workpress assembly of a high-speed IC handler. The frame attaches to a workpress assembly. Utilizing the clamp of a test socket recycles frequently unused test socket parts and eliminates the need for custom fabricated workpress assembly components. The method for adapting the hand test socket for use on the workpress assembly includes the steps: providing a test socket having a base and a top cover, the top cover including a clamp; removing the top cover and the clamp; configuring the clamp for use in a workpress assembly; and attaching the clamp to the workpress assembly.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: August 29, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Mark P. Kelley, Yakov A. Bobrov
  • Patent number: 6104876
    Abstract: A technique for providing PCI bus mastering compatibility for legacy PCI bus devices which may not support PCI bus mastering RETRY protocols. DLDMM provider software in a device driver for a target device may provide a callback signal at a callback address to DLDMM client software in a device driver for a bus mastering PCI device. The callback address may be used by the DLDMM client software to signal the bus mastering PCI device to suspend operation in the event of an interrupting event. The bus mastering PCI device may then generate in driver software a RETRY signal to the device driver of the target device. If the interrupting event is over, a signal may be sent by the DLDMM provider software in response to the RETRY signal to the DLDMM client software indicating that the bus mastering device may resume operation. The bus mastering device may then resume operation where left off.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 15, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Daniel Daum, Jeffrey G. Ort