Abstract: A phase comparator compares phase of a clock signal and a generated comparison clock signal based upon rising edges. The output of the phase comparator may include a series of short up (U) pulses or down (D) pulses, depending whether the phase of the comparison clock is leading or lagging the clock. Up and down pulses U and D control an up/down shift register which in turn compensates phase difference by inserting or removing additional discrete delay elements in a variable delay line. Based upon delay signals generated by the variable delay line, a double frequency clock generator generates a 2.times. clock signal. The 2.times. clock signal is divided by 2 in a divider to supply the phase comparator with the generated comparison clock signal. The feedback scheme helps the digital delay lock loop of stabilize after a few clock cycles without additional external control.

Abstract: A cloud radar apparatus is mounted on a portable containerized unit, a number of which may be located at various positions throughout the planet. Cloud radar data from each unit are periodically measured and stored and made available to researchers, upon request, through the Internet or other network. The system comprises two computers operating on different operating systems. A first computer uses a first operating system which allows it to readily interface with various radar equipment using an IEEE 488 interface or the like, to monitor the health of the equipment and operate the equipment. A second computer system uses a second operating system in a multi-user mode which allows it to readily access and manipulate data files and transfer data over the network. Communication between the two computers is achieved by allowing the first computer to log into the second computer as one of the multiple users. The first computer may upload data to the second computer using a FTP protocol or the like.

Abstract: The accuracy of multilateration systems can be greatly improved by using a correction method based on the SLS (Sideband Lobe Suppression) signal produced by a Secondary Surveillance Radar (SSR). Multilateration is a cooperative surveillance technique for aircraft equipped with Air Traffic Control Radar Beacon System (ATCRBS), Mode S, or Automatic Dependent Surveillance Broadcast (ADS-B) transponders. When one of these transponders aboard a vehicle is interrogated, it responds by broadcasting a message based on what the interrogation requests. These reply messages may be multilaterated to determine the source position of the transmission. Multilateration is a Time Difference of Arrival (TDOA) technique similar to triangulation. Multilateration can be performed to locate the transmission source of any SSR signal.

Abstract: An integrated circuit such as a video controller may be provided with core logic circuitry using CMOS technology which may be operated at different supply voltages such as 3.3 or 5 Volts. At lower supply voltages, the CMOS circuitry may run slower. For a video controller, certain higher resolution, pixel depths, and refresh rates may require high speed operation of the video controller. A monitoring circuit monitors the video mode, pixel resolution, pixel depth, and refresh rate and determines which supply voltage may be used to operate the video controller at such levels. An output signal from the monitoring circuit may be used by a switching circuit to supply an appropriate supply voltage to the integrated circuit. At lower performance levels, the integrated circuit may be operated at lower voltages to conserve power.

Abstract: The invention concerns a versatile mill, particularly the construction of its drive, central and clamping part with the fitting of knives, and the cooling of the milling part. The versatile mill is intended for processing food products and other organic and inorganic substances in the sense of milling, chopping, grinding, mixing or disintegrating the parts inserted into it in an enclosed processing system.

Abstract: A graphics controller circuit in a computer system for generating display signals to a television. The graphics controller circuit may downscale a display image to generate a downscaled image. While downscaling, the graphics controller circuit may generate each horizontal line of a downscaled image from a different number of horizontal lines of a display image. In addition, the graphics controller circuit uses clock signals with different frequencies so as to generate each horizontal line of the downscaled image in the same amount of time. The clock frequencies are designed to generate downscaled image horizontal lines at an input rate required for a television. In effect, the graphics controller circuit may avoid dropping display image horizontal lines while downscaling, and also reduce flicker while displaying the downscaled image on a television.

Abstract: A PCMCIA host adapter includes the capability to master a non-DMA system bus and control a DMA data transfer between a DMA capable peripheral and the internal system memory. A peripheral can be coupled to the system through a PCMCIA card plugged into a PCMCIA expansion slot. A DMA controller coupled to the PCMCIA expansion slots through a PCMCIA bus controls a DMA transfer between the internal system memory and the peripheral. A bus master disables the CPU and takes control of the system bus during a DMA data transfer. In an alternative embodiment, the PCMCIA host adapter can be used with either a system having a system bus with DMA capability or with a system having a system bus without DMA capability. In this alternate embodiment if the system bus has DMA capability, the PCMCIA host adapter effectively passes the DMA signals between the peripheral and the system bus.

Abstract: A built-in self test (BIST) for an integrated circuit (IC) including a large logic section, a large dynamic random access memory (DRAM), and a smaller static RAM (SRAM). Additional logic circuitry is included within the IC to enable the IC to test the DRAM, that is, a built-in self test of the DRAM. The DRAM test program is stored in the SRAM by the VLSI tester, and portions of the existing logic circuitry may be used for the memory testing. The VLSI tester initiates the DRAM test and inspects the results of the test but does immediately participate in the DRAM testing. Thereby, a VLSI tester can test both the logic and DRAM portions of the IC, eliminating the need for separate memory test equipment.

Abstract: This invention provides a method and apparatus for detecting common spans within one or more data blocks by partitioning the blocks (FIG. 4) into subblocks and searching the group of subblocks (FIG. 12) (or their corresponding hashes (FIG. 13)) for duplicates. Blocks can be partitioned into subblocks using a variety of methods, including methods that place subblock boundaries at fixed positions (FIG. 3), methods that place subblock boundaries at data-dependent positions (FIG. 3), and methods that yield multiple overlapping subblocks (FIG. 6). By comparing the hashes of subblocks, common spans of one or more blocks can be identified without ever having to compare the blocks or subblocks themselves (FIG. 13). This leads to several applications including an incremental backup system that backs up changes rather than changed files (FIG. 25), a utility that determines the similarities and differences between two files (FIG. 13), a file system that stores each unique subblock at most once (FIG.

Abstract: A graphics controller circuit comprising a plurality of pipelines for performing a set of operations on a stream of input pixel data to generate at least a first operand and a second operand. A rasterop unit in the graphics controller circuit may receive the first operand and the second operand, and execute a raster operation using the first operand and the second operand to generate a set of display pixel data. The graphics controller circuit may further comprise a transparency unit for generating a write enable mask corresponding to the set of display pixel data. A display memory may selectively store or block the set of display pixel data according to the write enable mask. As the graphics controller generates display signals from the display data stored in display memory, a transparency operation may be performed.

Abstract: A CD-R controller for recording on a CD-R disk a signal representative of a set of signal data. The CD-R controller includes a buffer manager for receiving a command such as a CUE-sheet, and sends the command to a micro-controller. The micro-controller generates instructions corresponding to each command by using information stored in a ROM. The buffer manager stores the instructions in a buffer and then sends the instructions to a CD-R formatter. Buffer manager may then send signal data corresponding to the instructions to a recording circuit. CD-R formatter generates control signals to the recording circuit from the instructions. The control signals cause recording circuit to generate recording signals to a CD-R drive. The CD-R drive may record the signal representative of the signal data in response to the recording signals.

Abstract: A method of adapting a hand test socket for use in a workpress assembly includes: providing a hand test socket having a base and a top cover. The top cover includes a clamp. The method includes the step: removing the top cover and the clamp and configuring the clamp for use in a workpress assembly. The step of configuring the clamp includes forming a frame and attaching the clamp to the frame.

Abstract: A multimedia system includes an audio/video decompresser/decoder for decompressing/decoding a compressed/encoded audio/video data stream in order to generate video images for display on a display device and to generate audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder that has a novel memory controller and a novel method for displaying complete decoded/decompressed video frames on a display device without tearing. By use of selective storage of decoded/decompressed video frames in memory, tearing is prevented but information for predicting motion of a video segment is preserved.

Abstract: A programmable filter is provided for filtering image or texture map data. A weighting RAM stores weighting data for filtering data in both x and y directions. Different weighting values may be programmed into weighting RAMs to provide different weighting functions and also enable or disable a number of taps within the filter. A weighting value of zero, for example, may disable a particular tap for the filter. In the preferred embodiment, a number of lines in the x direction may be simultaneously weighted and then weighted and combined in the y direction to produce a filtered value within one clock cycle.

Abstract: A descrambler for a Digital Versatile Disk (DVD) is provided within a DVD controller to allow for real-time descrambling of DVD data from the DVD buffer. The built-in descrambler also allows the controller to interface with a Host Adapter (e.g., ATAPI Host) or MPEG II decoder. The descrambling circuit reads four bits of an identifier portion of each sector. These four bits are used to access a look up table LUT in the descrambler for retrieving a 15 bit seed. The fifteen bit seed is used to generate a descrambling patter, which, when XORed with scrambled data, will descramble data on a byte-by-byte basis. The descrambling pattern is generated on a flash basis, by performing eight shift operations and XOR operations simultaneously, allowing for descrambling one byte per clock cycle.

Abstract: A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable.

Abstract: Short-circuit current and power consumption for an integrated circuit may be calculated by measuring short-circuit current for various cells within an integrated circuit using a Verilog.TM. logic level model of the cell. Each cell within an integrated circuit may be characterized by its inputs and outputs and connectivity. A corresponding SPICE sub-circuit model having the same logic characteristics as the cell may be generated. A number of calculation passes are made for each sub-circuit within a cell to determine short circuit current for each sub-circuit at various signal rise and fall times and for various inputs and outputs. Current data may be stored in a format compatible with Verilog.TM. propagation delay data. Overall power consumption and short circuit current for an integrated circuit may then be calculated from Verilog.TM. logic model data. The use of the Verilog.TM. model eliminates the need to calculate short circuit current at a SPICE circuit level.

Abstract: An input circuit to a semiconductor device may selectively accept different voltage logic levels (e.g., TTL or CMOS) as selected by a preset selection signal. The selection signal activates an N-type or P-type transistor in the input circuit which alters the threshold switching voltage of the input circuit logic. By altering the input threshold voltage, both TTL and CMOS input signals may be correctly triggered. An additional circuitry may be provided to allow a low voltage circuit (e.g., 3.3 Volts) to be tolerant of higher voltage inputs (e.g., 5 Volts). An isolation transistor isolates the input of the circuit from the high voltage signal, while a pulldown transistor pulls a high logic, high voltage signal down to supply voltage level.

Abstract: The display controller of the present invention reduces power consumption by suppressing clock signals to a display memory (comprising SGRAM or SDRAM) between screen refreshes and memory accesses. The present invention takes advantage of power-down modes provided for SGRAM and/or SDRAM memories which are used in the prior art to place a memory in an active suspend mode. Further energy savings are realized and memory bandwidth increased when using a display memory comprising two banks. When one bank of memory is being accessed, the other bank of memory is precharged and activated. Succeeding pages of memory are placed in alternate banks of display memory. Thus, then data is to be accessed from a next page of memory, the corresponding bank is already charged and ready to be accessed.

Abstract: The apparatus of the present invention includes a frame for attaching the clamp of a hand test socket to a workpress assembly of a high-speed IC handler. The frame attaches to a workpress assembly. Utilizing the clamp of a test socket recycles frequently unused test socket parts and eliminates the need for custom fabricated workpress assembly components. The method for adapting the hand test socket for use on the workpress assembly includes the steps: providing a test socket having a base and a top cover, the top cover including a clamp; removing the top cover and the clamp; configuring the clamp for use in a workpress assembly; and attaching the clamp to the workpress assembly.