Abstract: Scan testing of logic circuitry is facilitated by providing register circuits, each having an input gate configured to selectively pass a data s signal applied to that register, a master stage configured to store a data signal passed by the input gate of that register, an interstage gate configured to selectively pass a data signal stored by the master stage of that register, and a slave stage configured to store a data signal passed by the interstage gate of that register. Inter-register gates are operatively arranged to selectively pass a data signal stored by the master stage of an associated respective first one of the registers to the master stage of an associated respective second one of the registers for storage by the master stage of that second one of the registers. During normal operation, circuitry is configured to alternately enable the input gates and the interstage gates, and to disable the inter-register gates.

Abstract: A programmable logic device is provided that allows a redundant row of programmable logic to be shifted into place to repair the device when a defect is detected in a row of programmable logic on the device. The redundant row is shifted into place by routing programming data into the normal logic and the redundant logic while bypassing the row of logic containing the defect. Switching circuitry may be used to direct programming data into the serial inputs of various data registers that are then used to load the programming data into the device. The patterns of programmable connections that are made between programmable logic regions on the device and vertical and horizontal conductors also allow redundant logic to be shifted into place. Some connections between the logic and the horizontal and vertical conductors may be identical within a column to facilitate shifting. Other connections may only partially overlap between respective rows.

Abstract: An electronic circuit tester (e.g., for testing integrated circuit wafers or packaged integrated circuits) is provided. The tester is preferably based on a relatively inexpensive computer system such as a personal computer and includes at least one high-precision clock circuit that is programmable with respect to frequency and number of clock pulses. The high-precision clock circuit is connectable to the circuit being tested to permit certain timing-critical tests to be performed, even though a large number of other data channels in the tester are controlled by a relatively low speed clock circuit. The tester also includes analog circuitry that can be programmed to provide various analog signals suitable for performing parametric testing on an electronic device under test.

Abstract: A programmable logic device memory array circuit is provided that contains a pair of associated combinable single-port memory arrays. The memory array circuit may have a variable depth and width. The combinable single-port memory arrays may be operated independently if desired. Alternatively, a pair of the combinable single-port memory arrays can be combined to form a dual-port memory array. When the single-port memory arrays are combined to form a dual-port memory array, circuitry from a first of the combinable single-port memory arrays is used to perform writing operations and circuitry from a second of the combinable single-port memory arrays is used to perform reading operations. The availability of the dual-port memory array capability allows users to implement circuits such as first-in-first-out buffers and other circuits that require the ability to perform concurrent read and write operations.

Abstract: A programmable logic device has logic array blocks (“LABs”) and interconnection resources. For interconnecting signals to, from, and between the LABs, the global interconnection resources may include switch boxes, long lines, double lines, single lines, and half- and partially populated multiplexer regions. The LAB includes two levels of function blocks. In a preferred embodiment, there is one four-input second-level function block for every four-input first-level function blocks. At least one tri-state buffer is provided in each LAB. Each tri-state buffer may receive a data signal either from one or more function blocks in the associated LAB or from one or more interconnection conductors adjacent to the LAB. The tri-state buffer may buffer one of the received data signals and apply the resulting buffered signal to one or more of the interconnection conductors adjacent to the LAB.

Abstract: Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

Abstract: Methods and apparatus for delivering and installing a new length of tubing between two sections of a patient's existing body organ tubing and at least partly outside of that existing structure. For example, the new length of tubing may be for the purpose of providing the patient with a coronary bypass. The new tubing may be an artificial graft, a natural graft (harvested elsewhere from the patient), or both. The new tubing is delivered to and installed at the operative site primarily by working through the patient's existing tubular body organ structure. This avoids the need for any significant surgery on the patient.

Abstract: A micro-catheter including an inner primary liner and a plurality of concatenated tubes is provided. The primary liner extends substantially from the proximal end to the distal end of the catheter. Each of the tubes has a respective inner surface that is fused to the outer surface of the primary liner. For each and every pair of tubes, the outer diameter of the more proximally located tube is equal to or greater than the outer diameter of the more distally located tube. Each of the tubes may have different physical properties and dimensions for making customized micro-catheter profiles.

Abstract: A programmable logic device has plural regions of programmable logic and a general-purpose interconnection network for conveying signals to, from, and between the regions. In addition to the general-purpose interconnection network, more direct interconnections are provided from outputs of each region to inputs of one or more other adjacent or nearby regions. At least some of these direct interconnections are preferably multiplexed with more conventional inputs to the other regions so that the input resources required for each region do not become excessive. The invention is particularly useful for devices which perform basic logic using sum-of-products (“Pterm”) logic. However, the invention is also useful in other types of devices such as those which perform basic logic using look-up tables.

Abstract: Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g.

Abstract: A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides aL substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

Abstract: Audio signal samples taken at different sampling rates are synchronized. A plurality of channels of audio data are sampled at different rates and recognizable synchronization data are added to selected samples of at least one channel of the plurality of channels.

Abstract: The design of logic for implementation in programmable logic array integrated circuit devices is facilitated by allowing various characteristics of modules in the logic design to be parameterized. Specific values for a parameter can be “inherited” by a logic module from other logic higher in the hierarchy of the logic design. Default values for parameters can also be provided. The user can design his or her own parameterized modules, and logic designs can be recursive, meaning that a logic module can make use of other instances of itself.

Abstract: An improved macrocell for sum-of-products logic allows independent selection of D or T flip-flop operation, inverted or non-inverted register input, and use of a product term in register input control. The macrocell circuitry for providing this enhanced functionality can be implemented using only a small number of transistors greater than the number typically used to implement less flexible prior art macrocells.

Abstract: An improved light-readable information recording disc is provided in which the optical data storage structure consists of either lands and pits or lands and bumps, in which the depth of the pits or the height of the bumps, respectively, is controlled to approximate one-half of the wavelength of the light striking the optical data storage structure. Unexpected and surprising improvements over conventional optical recording discs is achieved through increased light intensity differences detected at the changeover between pits/bumps and lands.

Abstract: In a compression release engine brake, electrically controlled mechanisms are provided to partly selectively control the positions or motions of the engine brake slave pistons which periodically open the exhaust valves in the associated internal combustion engine when engine braking is desired. The electrically controlled mechanisms can be used for such purposes as controlling the "lash" of the engine brake or controlling the timing and duration of exhaust valve openings. Because these mechanisms are electrically controlled, they can be made to operate substantially instantaneously.

Abstract: The invention relates to an apparatus for separating finer and coarser material fractions of bulk material from each other, especially for separating sawdust from wood chips, the apparatus comprising a plurality of successive rollers (2) rotating about parallel axes of rotation, the upper surfaces of the rollers providing a path for the material to be screened; and a hopper for feeding the material to be screened to the infeed end of the path. There are radial and essentially axial grooves (5, 6) on the surface of the rollers (2), the grooves forming teeth (7) onto the surface of the rollers (2), and the teeth (7) of each roller (2) interdigitate with the radial grooves (5) of the adjacent roller (2), whereby the teeth (7) and radial grooves (5) form slots (8) between them for the particles of the material to be screened. With this construction it is possible to prevent the particles that are bigger than the grain size desired from passing through the screen.

Abstract: A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: A pallet system for supporting a workpiece (such as an electric motor stator or rotor) during processing of the workpiece includes a pallet member on which a workpiece holder can be removably placed. The workpiece holder may have multiple workpiece-engaging sites, each of which is adapted to hold a differently configured workpiece, and multiple pallet-engaging sites, each of which is associated with a respective one of the workpiece-engaging sites and any one of which can be used to engage the pallet so that the workpiece holder can hold a workpiece of the appropriate configuration at the associated workpiece-engaging site. Methods and apparatus for storing and manipulating the workpiece holders are also disclosed.