Patents Represented by Attorney, Agent or Law Firm Robert S. Babayi
  • Patent number: 5497490
    Abstract: A computer unit and multiple I/O adapter units are interconnectable in a variety of different plug attachment configurations which may be frequently altered in normal use of the system. An arrangement is provided for automatically initializing adapter units which are currently connected to the computer unit to operating states uniquely suited to the current configuration of connections. In the arrangement, non-volatile storage means retentively stores multiple sets of configuration state information, each set corresponding to a different configuration of connections between the adapter units and the computer unit. Means operating during each initialization of the system detects identities (ID's) of adapter units currently connected to the computer unit, and compares them to ID's associatively stored with the configuration state information.
    Type: Grant
    Filed: July 8, 1992
    Date of Patent: March 5, 1996
    Assignee: International Business Machines Corporation
    Inventors: Naoki Harada, Ken Inoue, Masahiko Shinomura
  • Patent number: 5495611
    Abstract: A personal computer system is disclosed which is compatible with application programs and operating system software. The personal computer system includes a microprocessor electrically coupled to a data bus, non-volatile memory electrically coupled to the data bus, volatile memory electrically responsive to the data bus, a memory controller electrically coupled to the microprocessor, the volatile memory and the non-volatile memory, and a direct access storage device electrically responsive to the data bus. The non-volatile memory stores a first portion of operating system microcode and the volatile memory includes a volatile operating system portion intended for use by the first portion of the operating system microcode. The memory controller regulates communications between the volatile memory, the non-volatile memory and the high speed microprocessor. The direct access storage device stores a second portion of operating system microcode which is accessed by the microprocessor as needed.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: February 27, 1996
    Assignee: International Business Machines Corporation
    Inventors: Richard Bealkowski, John W. Blackledge, Jr., Douglas R. Geisler, Michael R. Turner
  • Patent number: 5481709
    Abstract: A personal computer system is disclosed which is compatible with application programs and operating system software. The personal computer system includes a microprocessor electrically coupled to a data bus, non-volatile memory electrically coupled to the data bus, volatile memory electrically responsive to the data bus, a memory controller electrically coupled to the microprocessor, the volatile memory and the non-volatile memory, and a direct access storage device electrically responsive to the data bus. The non-volatile memory stores a first portion of operating system microcode and the volatile memory includes a volatile operating system portion intended for use by the first portion of the operating system microcode. The memory controller regulates communications between the volatile memory, the non-volatile memory and the high speed microprocessor. The direct access storage device stores a second portion of operating system microcode which includes a plurality of modules.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: January 2, 1996
    Assignee: International Business Machines Corporation
    Inventors: Richard Bealkowski, David E. Blaschke, Mary M. Bolt, Douglas R. Geisler, Robert G. Hillis, Frank J. Schroeder
  • Patent number: 5475871
    Abstract: A communications system (10) comprising a base station (12) for controlling a control channel signal and a plurality of traffic channels and a communications device (17) responsive to the control channel signal (16) and receptive to the plurality of traffic channels. The communications device comprises a tuneable filter (48), having an adjustable characteristic, which substantially filters all but a selected traffic channel of the plurality of traffic channels. The communications device further comprises a tuning circuit (24, 38, 40, 44, 46, 52) for adjusting the filter characteristic. The tuning circuit (24, 38, 40, 44, 46, 52) uses the control channel signal (16) as an accurate central frequency (F.sub.o) for a passband of the tuneable filter (48) and adjusts the filter characteristic to substantially a minimum insertion loss at the accurate central frequency, thereby substantially optimizing selectivity and sensitivity for the communications device (17).
    Type: Grant
    Filed: August 25, 1993
    Date of Patent: December 12, 1995
    Assignee: Motorola, Inc.
    Inventors: Doron Shalev, Gadi Shirazi
  • Patent number: 5465333
    Abstract: An apparatus is disclosed for processing information including a bus, a controller circuit, the controller circuit being configured to control transfer of information over the bus, and a slave circuit. The slave circuit includes a slave timing circuit which variably generates a ready signal indicating when the slave can accept data to allow the slave circuit to function in computer systems having different bus speeds. The controller circuit and the slave circuit exchange information via the bus at a speed controlled by the ready signal.
    Type: Grant
    Filed: February 15, 1995
    Date of Patent: November 7, 1995
    Assignee: International Business Machines Corporation
    Inventor: Howard T. Olnowich
  • Patent number: 5465357
    Abstract: A personal computer system is disclosed which is compatible with application programs and operating system software. The personal computer system includes a microprocessor electrically coupled to a data bus, non-volatile memory electrically coupled to the data bus, volatile memory electrically responsive to the data bus, and a direct access storage device electrically responsive to the data bus. The non-volatile memory stores a first portion of operating system microcode and stores a load indicator. The direct access storage device stores the second portion of operating system microcode which is loaded into the volatile memory by the inialization program based upon the load indicator.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: November 7, 1995
    Assignee: International Business Machines Corporation
    Inventors: Richard Bealkowski, Douglas R. Geisler, Michael R. Turner
  • Patent number: 5459842
    Abstract: A write compression buffer is connected to a CPU bus and to a memory controller to provide write cycle compression in which plural partial write requests to the same memory address are compressed into a single memory write cycle. The buffer has a plurality of buffering level.
    Type: Grant
    Filed: June 26, 1992
    Date of Patent: October 17, 1995
    Assignee: International Business Machines Corporation
    Inventors: Ralph M. Begun, Paul W. Browne, Marc R. Faucher, Gerald L. Frank, Christopher M. Herring
  • Patent number: 5453581
    Abstract: A pad arrangement (100) for aligning and attaching a surface mount component (402) with other circuitry includes a substrate (102) upon which opposing pads (108) are attached. Each of the pads occupies a substantially rectangular area (110) having four sides. In order to facilitate alignment of the surface mount component the substantially rectangular area has two opposing flat sides an outwardly extending arcuate area (112) along at least one of the other two sides.
    Type: Grant
    Filed: August 30, 1993
    Date of Patent: September 26, 1995
    Assignee: Motorola, Inc.
    Inventors: Henry F. Liebman, Peter E. Albertson
  • Patent number: 5452470
    Abstract: A data communication system contains a dual-port/dual-access-mode storage subsystem, and a communication controller connecting between that subsystem and external data communication channels. The storage subsystem includes one or more dual-port/dual-access mode storage devices consisting of a pair of random access and sequential access memory arrays, with a parallel block transfer connection between the arrays. The sequential access array can store a large block of up to N bytes (N for example equal to 256), and the random access array can store multiple such blocks. The subsystem also has RAM and SAM access ports respectively controllable in random access and sequential access modes and respectively connecting to the random access and sequential access arrays.
    Type: Grant
    Filed: August 23, 1994
    Date of Patent: September 19, 1995
    Assignee: International Business Machines Corporation
    Inventors: Robert F. Kantner, Jr., Tze-Wing Keung, Jace W. Krull, Shahram Salamian
  • Patent number: 5450551
    Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU) connected to system memory by a first system bus, and a second system bus connected to the CPU; (ii) a host bridge connecting the second system bus to a peripheral bus; (iii) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto; and (v) arbitration logic which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: September 12, 1995
    Assignee: International Business Machines Corporation
    Inventors: Nader Amini, Patrick M. Bland, Bechara F. Boury, Richard G. Hofmann, Terence J. Lohman
  • Patent number: 5450458
    Abstract: Data transfer between subsystems of an information handling system employing a multiple subsystem clock environment architecture, or between multiple information handling systems operating with different clock frequencies, is synchronized using a timing aligned multiple frequency synthesizer with a synchronization window decoder. A frequency generation circuit in circuit communication with a data synchronization circuit functions to produce a synchronized timing signal(s) to permit a central processing unit operating in one subsystem clock environment to function with a peripheral subsystem(s), such as a memory controller, operating in a different subsystem clock environment, or permits information handling systems operating with different clock frequencies to function with one another. Data transfer synchronization delays are reduced and mean-time-to-failure of signal synchronization accuracy is increased by eliminating metastability effects from the synchronization circuitry.
    Type: Grant
    Filed: August 5, 1994
    Date of Patent: September 12, 1995
    Assignee: International Business Machines Corporation
    Inventors: Warren E. Price, Kenneth A. Uplinger
  • Patent number: 5448703
    Abstract: A device for generating back-to-back data transfers on a bus in an information handling system. A detector for determining whether a first address value and a second address are within a range, a first register connected to the detector for storing the first address until the device generates the second address, a second register connected to the detector for storing the range value, and a transfer state block for driving the second address on the peripheral bus without a turnaround cycle if the detector determines that the first and second addresses are within the range. Thus, back-to-back data transfers are provided.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: September 5, 1995
    Assignee: International Business Machines Corporation
    Inventors: Nader Amini, Ashu Kohli
  • Patent number: 5446898
    Abstract: A personal computer system which is compatible with application programs and operating system software is disclosed. The personal computer system includes a microprocessor electrically coupled to a data bus, non-volatile memory electrically coupled to the data bus, volatile memory electrically responsive to the data bus, a memory controller electrically coupled to the microprocessor, the volatile memory and the non-volatile memory, and, a direct access storage device electrically responsive to the data bus. The non-volatile memory stores a first portion of operating system microcode and request information which indicates whether a second portion of operating system microcode is required by the personal computer system. The volatile memory includes a volatile operating system portion intended for use by the first portion of the operating system microcode. The memory controller regulates communications between the volatile memory, the non-volatile memory and the high speed microprocessor.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: August 29, 1995
    Assignee: International Business Machines Corporation
    Inventors: Richard Bealkowski, Mary M. Bolt
  • Patent number: 5434592
    Abstract: A multimedia solution is presented which allows a multimedia architecture to be implemented on an existing computer system. According to the invention, an expansion unit which incorporates a multimedia architecture is provided. The expansion unit is connected to an existing computer system via an expansion slot of an I/O bus of the existing computer as well as via a display device output terminal of the computer. The expansion unit is also connected to a display device. Accordingly, the expansion unit controls the presentation which is provided on the display device.
    Type: Grant
    Filed: September 17, 1993
    Date of Patent: July 18, 1995
    Assignee: International Business Machines Corporation
    Inventors: John M. Dinwiddie, Jr., Bobby J. Freeman, Thomas J. Micallef, Gustavo A. Suarez, Bruce J. Wilkie
  • Patent number: 5434590
    Abstract: An information handling apparatus for transferring and composing image signals including a plurality of media sources configured to provide a corresponding plurality of image signals, a media bus connected to the media sources, and a media control module coupled to the media bus. The media bus allows selective access for the plurality of image signals. The selective access enables composition of the independent image signals in response to control information. The media control module receives a composed image signal from the media bus and provides the composed image signal to a display device.
    Type: Grant
    Filed: October 14, 1993
    Date of Patent: July 18, 1995
    Assignee: International Business Machines Corporation
    Inventors: John M. Dinwiddie, Jr., Bobby J. Freeman, Gustavo A. Suarez, Bruce J. Wilkie
  • Patent number: 5410699
    Abstract: An apparatus and method for loading BIOS from a diskette drive into a personal computer system normally connected to a hardfile, such as a fixed disk. The personal computer system further includes a system processor, a random access main memory, a read only memory and a switching means. The switching means generates a signal to indicate a mode for whether BIOS loads from either diskette or disk. In a priority mode, BIOS loads immediately from diskette. In a recovery mode, BIOS loads from diskette after testing the disk subsystem.
    Type: Grant
    Filed: November 2, 1990
    Date of Patent: April 25, 1995
    Assignee: International Business Machines Corp.
    Inventors: Richard Bealkowski, John W. Blackledge, Jr., Doyle S. Cronk, Richard A. Dayan, Scott G. Kinnear, George D. Kovach, Matthew S. Palka, Jr., Robert Sachsenmaier, Kevin M. Zyvoloski
  • Patent number: 5404471
    Abstract: A data processing system has a microprocessor that is operable in real and protected address generation modes. Transition from the real mode to the protected mode is done by initializing system tables and pointer registers, switching from the real mode to the protected mode, and flushing a prefetch queue before executing further instructions in the protected mode. The transition also includes flushing instructions from the prefetch queue, immediately after the initializing, and executing at least one instruction while prefetching additional instructions that are executed to complete the transition.
    Type: Grant
    Filed: February 8, 1993
    Date of Patent: April 4, 1995
    Assignee: International Business Machines Corp.
    Inventors: Seiichi Kawano, Hirohide Komiyama, Shuichi Mukohyama
  • Patent number: 5396602
    Abstract: An arbitration mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; (iii) a second system bus connected to the CPU; (iv) a host bridge connecting the second system bus to a peripheral bus, the peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: March 7, 1995
    Assignee: International Business Machines Corp.
    Inventors: Nader Amini, Patrick M. Bland, Bechara F. Boury, Richard G. Hofmann, Terence J. Lohman
  • Patent number: D360409
    Type: Grant
    Filed: May 24, 1994
    Date of Patent: July 18, 1995
    Assignee: International Business Machines Corporation
    Inventors: Roland K. A. Alo, Jr., Richard F. Sapper, Brian Trumbo
  • Patent number: D362238
    Type: Grant
    Filed: May 24, 1994
    Date of Patent: September 12, 1995
    Assignee: International Business Machines Corporation
    Inventors: Roland K. A. Alo, Jr., Jeffrey W. Benck, Fred E. Goetz, Richard F. Sapper