Abstract: A frequency synthesizer circuit, having first and second modes of operation, comprises a voltage-controlled oscillator (VCO) (64), a low-pass filter (74), a phase-locked loop (PLL) (67), an analog-to-digital converter (50), a digital-to-analog converter (56), a controller (48), and a VCO input switch. During the first mode, the VCO input switch couples the control input of the VCO to a control signal produced by the PLL, and the analog-to-digital converter measures the control signal and provides it to the controller which stores the control voltage measured by the analog-to-digital converter. During the second mode, the VCO input switch couples the control input of the VCO to the digital-to-analog converter which applies the stored control to the control input of the VCO.

Abstract: A DMA controller with error circuitry which detects DMA error conditions is disclosed. The error circuitry causes the DMA controller to perform completion tasks before terminating a DMA transfer, advantageously providing a DMA controller which may exit gracefully upon detection of an error condition with the potential of error recovery.

Abstract: A tunable oscillator circuit (200) includes surface acoustic wave transducer (303) disposed on a piezoelectric substrate (301) having a high SAW coupling coefficient. The SAW transducer is (303) non-reflective and self-resonant comprising a pair of electrodes with interdigitated fingers. A tuning mechanism, such as a varactor, is coupled across the transducer allowing for output frequency tuning of the oscillator circuit.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: A communication unit (10) transmits a first signal (12) that has a plurality of holes (44) therein during the occurrence of which another communication unit may interrupt. A repeater (14) receives the first signal and transmits a second signal (16) comprising the information in the first signal, and a plurality of digital coded squelch words synchronized with the holes to indicate the location of at least one of the holes in the first signal (i.e., the time at which at least one of the holes will occur). In one embodiment, each hole occurs after each pair of coded squelch words, and accordingly the pairs of coded squelch words are marked to indicate the times of occurrence of holes in the first signal.

Abstract: A bandpass filter, having an input port and an output port, comprises a first microstrip split-ring resonator coupled to input port, and a second microstrip split-ring resonator coupled to the first microstrip split-ring resonator, and coupled to the output port. A lumped or distributed capacitance is disposed between the first microstrip split-ring resonator and the second microstrip split-ring resonator.

Abstract: In a computer system having a CPU and several buses which includes a system bus and an I/O bus, parity error can occur when data is being written between the I/O bus and the system bus. This invention provides a technique for detecting whether a parity error has occurred on data being written between the system bus and the I/O bus. If a parity error is detected, the address at which such error occurred is stored and then sent on to the system bus to the CPU.

Abstract: System non-maskable interrupts are detected by an override controller which initiates an NMI routine override operation. During override, address requests for an standard NMI routine are intercepted, and instead a predetermined memory space is addressed that contains a system specific NMI trace routine. The processor is unaware that the override controller has inserted the system specific NMI routines. The processor executes the system specific NMI routines, and when the specific routines are completed, the override controller generates a termination signal which returns program control back to the standard NMI routine. The system specific NMI routine is designed to trace errors created by new system functions or hardware or to enhance the error tracing capability for existing system functions.

Abstract: A noise squelch circuit for a radio receiver (100) includes an adaptive filter (204) for shaping frequency characteristics of a demodulator out put (115) according to factors which effects squelch sensitivity. Such factors may include channel spacing of the receiver, received signal strength level, received signal deviation, and SINAD. The adaptive filter (204) comprises a switched capacitor filter, the response of which may be controlled by a control signal (212) according to one or more of such factors.

Abstract: An arbiter with an arbitration hold feature is provided which makes it possible to begin an arbitration cycle while information is still being transferred via a bus because the arbiter does not reallocate the bus until the present transfer is complete, as indicated by the arbitration hold feature. Accordingly, arbitration can essentially be overlapped with transfer of information over the bus, thus increasing the amount of information which can be transferred in a given interval of time.

Abstract: In a CDMA communication system (100) capable of communicating between a receiver (20) and a transmitter (10) direct sequence spread spectrum communication signals (30), a system and method for synchronizing receiver bit timing and transmitter timing. Transmitter (10) transmits a training bit sequence (31) followed by a transmitter bit timing sequence (33). The receiver (20) adaptively determines a representation of a despreading chip sequence using a tapped delay line equalizer (400). Receiver bit timing offset is determined based on the representation of the despreading chip sequence and the transmitter bit timing sequence (33).

Abstract: In a radio transceiver (100), an IF stage (110) is formed on a single substrate. A balanced or image rejection mixer (204) having two pairs of inputs and a pair of outputs is integrated on an IC substrate (202). Disposed on the IC substrate are SAW transformers (210, 212 and 214) which provide a desired phase transformation. The SAW transformers comprise piezoelectric layers (228) and metallization layers (230) which are suitably patterned to provide the desired phase transformation and frequency selectivity.

Abstract: Epoxy bonding between an IC chip and a chip carrier is strengthened by creating substantially rougher oxidized surfaces within substantially smooth gold surfaces of a die paddle portion of the chip carrier.

Abstract: A battery charger (230) is provided for charging a battery (210) at high temperatures. The charger (230) includes a thermistor (236) for monitoring the ambient temperature and a rapid charger (232) for providing the charge current to the battery. When the ambient temperature exceeds a high threshold temperature and when the battery (210) needs to be charged at this temperature, the battery charger (230) rapid charges the battery until the battery temperature reaches a cut-off temperature. The cut-off temperature is a temperature having a fixed level above the ambient temperature.

Abstract: An apparatus for reducing audio interference produced by a transducer (18) in response to an audio signal has a first input for receiving the audio signal and a second input (22) for receiving sound signals. The audio interference affects a speech recognition system (34). The second input provides a possibly contaminated signal representing the sound signals. The sound signals comprise a desired audio signal, and possibly comprise the audio interference. An interference reduction device (30) is coupled to the first and second inputs, for transforming the possibly contaminated signal into features that are substantially free from the effects of the audio interference.

Abstract: A transmission line structure (100) is provided which includes a resonator (110) having open ends (118) disposed on a substrate (130). The first resonator (110) includes a control voltage terminal (116) which is positioned at a point along the length where a zero potential exists at resonant frequency. Transmission zero frequency is tuned by means of a varactor (150) which is coupled to the control voltage terminal and receives a control voltage for controlling the zero frequency.

Abstract: In a TDM communication system (100), full duplex communication is provided for two communication units(104) and (105) which communicated communication messages through a repeater (102). Communication messages transmitted from the communication units (104) and (105) are combined in the repeater (102) to produce a combined communication message. The repeater (102) transmits the combined communication message to the communication units (104) and (105). The communication units (104) and (105) remove from the combined communication message the communication the previously transmitted communication message so as to recover the communication message from the other communication unit.

Abstract: A bow sight includes a plurality of individually adjustable sight pins capable of longitudinally moving along a bow sight track. Each sight pin is extended form a sight pin carrier which includes a user activatable locking means. Upon activation, the sight pin carriers are locked to the track preventing movement of the sight pin carrier. A rotatable threaded shaft is positioned within the track, which upon rotation by a knob moves an unlocked one of the sight pin carriers along the track. Therefore, an archer may individually adjust a desired sight pin by unlocking its sight pin carrier and rotating the knob.

Abstract: A power supply (100) includes an energy source (102) which provides cyclically varying supply voltage having periodic repeated beginning points. Generally, the beginning points comprise zero potential points of the cyclically varying supply voltage. The energy source is coupled to an energy control means (106) which is responsive to a control setting for controlling an output (108). A controller (114) provides the control setting in response to a feedback signal received from a sensor (116) only at the beginning points and maintains control of the control setting constant until a subsequent beginning point.