Abstract: A complementary Lateral Insulated Gate Rectifier (LIGR) includes two complementary LIGR structures fabricated in adjacent surface-adjoining semiconductor wells of the same conductivity type in a semiconductor substrate. The two LIGR structures are of generally similar configuration, thus simplifying the manufacturing process, and the proposed design additionally permits the n-channel and p-channel LIGR structures to have comparable "on" resistances. The two LIGR structures, otherwise isolated by a portion of the substrate separating the two semiconductor wells, are connected together by a common source electrode. The resulting complementary Lateral Insulated Gate Rectifier features a compact, integrated structure in which the "on" resistances of both the n-channel and p-channel portions of the device are comparable.

Abstract: An electro-acoustic arrangement comprises an amplifier (4) having a first input terminal (5), a second input terminal (5'), a first output terminal (3), a second output terminal (3'), and a series arrangement of a first impedance (1) and an electro-acoustic transducer unit (2) is coupled to the output terminals (3, 3'). At least the first impedance (1) is also coupled to the input terminals (5, 5') of the amplifier. The gain factor (A) of the amplifier for a signal applied to the first and second input terminals (5) and/or the impedance value Z.sub.1 of the first impedance may be variable. This arrangement influences the acoustic properties of a space, such as the reverberation time. By means of such an arrangement (FIG. 1) and in particular by means of a system (FIG. 9) comprising a plurality of such arrangements, the acoustic properties of a space, such as the reverberation time, can be influenced.

Abstract: A current-discrimination arrangement, in particular for use in stabilizing circuits, comprises two cross-coupled transistors. The current to be discriminated is applied in parallel to both transistors. For small currents both transistors conduct to the same extent, while at a current I=2(KT/qR), in which R is the resistance value of the collector load impedances of the two transistors, the circuit becomes bistable. The steep characteristic at the transition from non-stable to the bistable operation is used as discrimination characteristic.

Abstract: A non-volatile storage cell has a floating conductive layer which is coupled to an injector region which is located in the semiconductor body and, viewed on the surface, is connected by a semiconductor zone entirely enclosed by a thick insulating layer to an electrode region of the storage transistor. The injector region is doped more weakly than the semiconductor zone and at least a part of the edge of the semiconductor zone follows in a self-registered manner an edge of the thick insulating layer. Furthermore, the floating conductive layer is located for at least half its size on the thick insulating layer.

Abstract: A method of forming a support wire for the arc tube of a discharge lamp wherein a cut end of the support wire is flattened to provide a smooth burr-free surface for insertion into the opening of the niobium tubes located at the ends of the arc tube of the discharge lamp.

Abstract: For increasing the sensitivity of an MR apparatus when measuring comparatively high frequencies, the radio frequency excitation measurement coil (10, 30) is divided into two individual symmetrically drivable and readable coil halves (32, 34), respectively. The mutual connection of central connections of the coil halves can be realized by means of a balun (54) but for this purpose any other symmetrical form of coupling, for example using a strip-line transformer (70) or suitably dimensioned coaxial cables (60, 62) may alternatively be used.

Abstract: The breakdown voltage of a p-n junction operated under reverse bias in at least one mode of operation of a semiconductor device is increased by providing at least one annular region forming an auxiliary p-n junction within the spread of a depletion layer from the reverse-biased junction. A passivating dielectric layer with an overlying electrically resistive layer extends over the semiconductor body surface between the active device region forming the p-n junction and a surrounding region of the body portion located beyond the (outer) annular region. The resistive layer is connected to these regions but is insulated from the annular regions by the dielectric layer. A stable high breakdown voltage can be obtained by providing the resistive layer with conductive connection means at the or each annular area which overlies the annular region(s).

Abstract: Charge-coupled devices are very sensitive to clock cross-talk due to the overlap between successive electrodes. The influence of this cross-talk is reduced when the clock lines are periodically connected to ground by a low-ohmic impedance. For this purpose, each clock line is controlled from a buffer, whose output is connected to a clock line. A clamping transistor is connected between the output and ground. When this clamping transistor is controlled by means of the output signal and at the same time by the input signal of the buffer, the output is clamped to ground at the instant at which the cross-talk is expected by means of only a single clamping transistor.

Abstract: The invention relates to a covering device for protecting the nozzle area of an ink jet writing head, which device is detachably connected to the ink jet writing head in a sealing manner and forms a cavity which is opened towards the nozzles, into which cavity liquid ink is transported through the nozzles. In order to be able to store and transport an ink jet writing head filled with liquid ink for a long period of time, in particular also as an individual component, for example as a spare part, without the possibility existing the liquid ink of drying in the nozzle area and without enclosed or penetrating air bubbles that can lead to a chemical change of the liquid ink, it is ensured that the covering device (7) is form-coupled to the ink jet writing head (1) and that the cavity (8) comprises a closable ventilation duct (12) which communicates with the atmosphere.

Abstract: The method and device for NMR Fourier zeugmatography utilizes amplitude-modulated r.f. pulses (90.degree. and 180.degree. pulses) for the excitation of nuclear spins and the generating of nuclear spin echo signals. For three-dimensional Fourier zeugmatography, r.f. pulse having a large bandwidth (for example 10-50 kHz) are desired. The use of amplitude-modulated signals then implies an undesirably high peak power of the r.f. generator. In accordance with the invention, use is made of a frequency-modulated signal which can have a substantially constant amplitude and which preferably covers the desired frequency spectrum at a uniform speed.

Abstract: An assembly for supporting a body having approximately a predetermined dimension, particularly a printed circuit board (1), comprises a frame (4, 11-14), at least one support member (9), and further support means, suitably another support member (10). An edge (5) of the body (1) is received in a groove (7) extending along and into the support member (9). The body (1) and frame (4, 11-14)comprise co-operating locating means such as a plug (2) and socket (3) which locate one end of the body (1).

Abstract: An improvement in telephone equipment which enables a user to cancel the wrong digit of a misdialed number regardless of its position in the number without cancelling other digits in the number.

Abstract: The invention relates to the determination of an NMR distribution in which an alternating gradient field is applied while sampling the NMR signal (FID signal, nuclear spin echo signal). The frequency of the alternating gradient field is comparatively low (order of magnitude of 100 Hz) and the field has from a few to some tens of cycles during each measurement period. While an FID signal is being sampled, the image frequency field matrix is scanned using a zig-zag (oscillating) line pattern during each line when data is provided for elements in from a few to some tens of rows in the image frequency matrix. By applying preparation gradient fields, the image frequency matrix can be filled by means of successive zig-zag line patterns which have been shifted with respect to one another and which thus enable a uniform sampling density to be provided in the image frequency space.

Abstract: A memory and a non-volatile, programmable, static memory cell in which a programmable transistor and a capacitance are added to a known static memory cell. The cross-wise couplings between the transistors of the static cell form a first and a second junction. The gate and a main electrode (drain) of the programmable transistor are connected to the first junction. The second junction is connected to an injection location opposite the floating gate of the programmable transistor whose channel is connected in series with the capacitance the other side of which is connected to the sources of the two transistors of the static cell.

Abstract: An electronic D-type flipflop includes two storage elements and two transmission gates wherein each gate includes only one MOS transistor. In the first gate the MOS transistor is of a first conductivity type and it is of a second conductivity type in the second gate. The MOS transistors each receive the same clock signal at their gate electrode. Because it is not necessary to form an inverted clock signal, problems due to phase differences between the clock signal and its inverse are precluded. Each of the storage cells includes a pair of inverters which are coupled end-around. The transmission characteristic of the forward inverting circuit is adapted in such a way that it compensates for the voltage drop across the preceding transmission gate. Only a small substrate surface area will be required when the flipflop is used in an integrated circuit.

Abstract: A clocked direct voltage converter with potential separation includes a control circuit for controlling the switching times of a switching transistor arranged on the primary side of the voltage converter, in which voltage converter voltage proportional to an output quantity is chopped by a controllable switch. The chopped voltage is transmitted by a transformer to the primary side of the converter, is then rectified, filtered and supplied to the control circuit. In order to obtain the largest possible control range for the converter, a further transformer is provided which transmits oscillation signal of an oscillator of the control circuit to the controllable switch on the secondary side voltage converter. By means of this oscillation signal, the controllable switch is controlled.

Abstract: A high-efficiency class-G type amplifier comprises a first transistor (T.sub.1), having its collector connected to a first supply voltage (V.sub.1) via a first diode (D.sub.1) and a second transistor (T.sub.2), connected in series with the first transistor and which has its collector connected to a second supply voltage (V.sub.2). The series arrangement of a second (D.sub.2), a third (D.sub.3) and a fourth diode (D.sub.4) is connected between the bases of the first and the second transistor (T.sub.1, T.sub.2) the fourth diode (D.sub.4) is poled in a direction opposite to that of the second (D.sub.2) and the third diode (D.sub.3). The series arrangement of a first resistor (R.sub.1) and the emitter-collector path of a first current-source transistor (T.sub.4) connects the second supply voltage to the anode of the fourth diode (D.sub.4). The junction point (5) between the first resistor (R.sub.1) and the current-source transistor (T.sub.4) is connected to the output (2) by means of a capacitor (C.sub.1).

Abstract: A D/A converter which converts a one-bit coded signal into an analog signal by means of an integrator comprising an operational amplifier (1) having an output (4) fed back to the inverting input (3) by means of a first capacitor (C.sub.1) and a resistor (R.sub.1). Depending on the value of the one-bit coded signal a positive current pulse or a negative current pulse is applied to the inverting input (3) of the integrator. The positive current pulses are generated by means of a switching network (10) comprising a second capacitor (C.sub.3) which is switched by means of a plurality of switches (S.sub.1 to S.sub.4). The negative current pulses are generated by means of a switching network (20) comprising a third capacitor (C.sub.4) which is switched by a plurality of further switches (S.sub.5 to S.sub.8). In order to ensure that the analog output signal is not distorted as a result of the positive and negative current pulses, a fourth capacitor (C.sub.2) is connected to the inverting input of the integrator.

Abstract: A substrate bias generator in which a junction point of the capacitance and the diode of a charge pump is connected to the ground point of the circuit (and of the further circuit on the substrate for which the bias is generated) via two or more series-connected transistors. During the charging period of the capacitance the transistors are (fully) conductive, hence the capacitance is optimally charged as the conductive transistors cause no (or hardly any) voltage drop. During the pumping cycle all transistors are diode-connected, to bring about a negative voltage with respect to the ground point at the junction point. This negative voltage is limited to the sum of the threshold voltages of the diode-connected transistors.

Abstract: A switching stage receives two levels at its input, i.e. a high selection level and a low non-selection level. The Darlington stage (T.sub.1, T.sub.2) supplies at its output (E) a high current in the selected mode and a considerably smaller current in the non-selected mode. In order to accelerate the evacuation of charges accumulated in the base of T.sub.2 and hence the deselection time of the stage, an auxiliary current source (I), is connected to a point A. Between the base (B) of the transistor T.sub.2 and the point A two diodes (D.sub.1, D.sub.2) are connected in series in the forward direction. Between the emitter (E) of T.sub.2 and the point A a diode (D.sub.3) is connected in the forward direction. In the selected mode, the major part of the current I passes through D.sub.1, D.sub.2 and this current permits the evacuation of the charges from the base of the transistor T.sub.2 when the stage is deselected.