Abstract: A modularized scanned logic test system includes modularized logic circuits (26) having control/observation locations therein. Each of the control/observation locations has a shift register latch (SRL) disposed thereat. A common scan data in line (28) provides data to a serial input to each of the modules (26). The serial output of each of the modules (26) is interfaced with a scan data out line (30). An address on a bus (16) is provided to a decoder (52) to select one of the modules (26). An isolation gate (48) allows for input of data to only the select one of the modules (26) and an isolation gate (50) allows output of data only from the select one of the modules (26) to the scan data out line (30).

Abstract: Video display of stored text is accompanied by associated speech from a speech synthesizer using coded sounds and intonation. A central processor controls selection of text and speech. Speech is selectable in one of a plurality of prestored languages coded in frequency and duration data.

Abstract: A transparent shift register latch (170) includes a normal operating gate (182) and a test gate (184) for selectively connecting data to a node (180). The node (180) is input to an isolation gate (186) through an inverter (188) for connection to an output node (190). A peripheral port (172) is interfaced with the output node (190) through an isolation gate (192). The gates (186) and (192) are operable in a test mode to interface data stored on the node (180) with the output of the latch (170) and inhibit input of data from the port (172). In the normal operating mode, the isolation gate (192) is closed and the isolation gate (186) is opened. The transparent shift register latch (170) allows testing of interface lines between adjacent logic modules.

Abstract: A single chip multiprocessor interface device for interfacing between two processors by connection to their bus systems, the device having a random access memory selectively accessible by the processors under the control of an arbitration latch. The arbitration latch has a bistable device the state of which determines which processor has access to the memory. The outputs of the bistable device have threshold devices which have threshold levels higher than the signal outputs of the bistable device when it is in a metastable state, so that there is no possibility that both processors could have access to the memory at the same time. Data and address registers for the two processors are selectively connectible to the random access memory through multiplexers controlled by the arbitration latch.

Abstract: A video system controller allows for the transfer of data between a display memory and a microprocessor that is used to control the controller and from the display memory to a CRT monitor. The transfer operations are controlled by the video system controller through a state machine that is configured with a plurality of standard cells connected in cascade arrangement, which can be configured as either a Moore or a Mealy state machine. Each state machine has a programmable logic array in which timing signals, when applied thereto, will cause a predetermined output to appear on the output on each of the standard cells. A logic means, depending upon whether the machine is a Moore type state machine or a Mealy type state machine logically manipulates the output of the programmable logic array to obtain the state output for that particular cell.

Abstract: A redundant column circuit includes a row shared predecoder (12) and predecoders (16), (18) and (20). The predecoders (16-20) are input to a one-of-sixty-four decoder (28) for providing sixty-four decoded outputs therefrom, each of which is input to a one-of-four multiplexer (30). Each of the multiplexers (30) selects one of four normal decode outputs and one of four redundant decode outputs. The selected decode output is determined by the four outputs from the row shared predecoder (12). A switch bank (32) of single pole double throw switches selects between a normal and a redundant output with the redundant output having the address associated therewith incremented by one. The output of the switches in the bank (32) is input to the deactivation circuits (36) for output therefrom to a memory array (38). The memory array (38) has a redundant column (R) in parallel therewith which is controlled by the first switch in the switch bank (32).

Abstract: A self testing ROM includes an information array (10) for storing data therein and a parity array (12) for storing associated parity information for each of the data words. The data is accessed and multiplexed for input to a block code error detect circuit (30) for detecting the error and outputting an error syndrome on a bus (32). The error syndrome is input to an error correct circuit (34) for correction of the accessed data during a first pass through the error detect circuit (30). This corrected data is then input to latches (39) and (41). The latched data is then input back to the block code error detect circuit (30) during a second pass to determine if the data was corrected. If not, this indicates that there were too many errors to be corrected by the error detection algorithm. This is detected with a system error detect circuit (43) during the second pass through the block code error detect circuit (30).

Abstract: In video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

Abstract: In a video computer system having a RAM chip with a shift register connected to its serial output terminal and actuated by a first clock circuit, a second different clock circuit is included to cause the data bit in the first stage of the register to also appear at the serial output terminal of the chip. Accordingly, signals from the first clock circuit will then sequentially transfer data bits from the shift register, to the output terminal of the RAM chip, without omitting or losing a clock cycle, or a portion thereof.

Abstract: A system for visualization on a video screen (6) in a graphical mode in which the visual information to be displayed is defined on the screen by a point by point sweeping, from page memory containing, at a given time, all of the video information to be displayed, and a video display processor (4), connected to a random access memory containing said page memory and to a display control unit (37) adapted to convert the information relative to the image composed from the contents of the memory (5) to screen (6) control signals, characterized in that central processing unit (1) is connected to the video display processor (4) by means of a single bus (12) over which are transmitted, on a time shared basis, the address fields and the data fields (15) and in that it includes in addition a control and interpretation circuit (27) capable, in response to an assignment signal generated by said central processing unit, to interpret the address field as an address field per se or as a control field for the video display p

Abstract: A semiconductor memory is comprised of four arrays (10), (12), (14) and (16) that have the memory elements therein arranged in accordance with pixel positions on a display. The memory arrays have associated shift registers (34), (36), (38) and (40) which have data loaded in parallel and output in a serial format to the display. Each of the shift registers can be connected in a circulating fashion or a shift register of adjacent arrays can be cascaded. Switches (56), (58), (60) and (62) are provided for configuring the shift registers for either circulation or cascading of data. In the circulating mode, the input and output of the shift registers is multiplexed on one pin whereas in the cascaded configuration, one array receives a dedicated serial input and the other array in the cascaded pair outputs the serial output on a dedicated pin.

Abstract: A data processing system has an arithmetic logic unit that includes a plurality of summation units for summing an ADDEND with a AUGEND to obtain a first signal that represents the summation of the ADDEND, AUGEND and a CARRY IN. Each summation units also provides a second signal that represents the carry of the summation of the ADDEND and the AUGEND. The plurality of summation units are arranged in a second plurality of groups of less than a third preselected number of summation units with over to the carry in such that each member group has a carry a serial connection of the carry in for receipt of a carry out from a preceding group's carry out. Interdisposed between the groups is a fourth plurality of carry boost units for boosting the second signal of a preceding group prior to application to a following group.Each summation unit includes a carry advance node which is driven to a predetermined voltage when the ADDEND and AUGEND do not indicate a carry propagate condition.

Abstract: A semiconductor memory comprises four arrays (10), (12), (14) and (16) disposed on a single semiconductor chip. Each of the arrays has a serial shift register (86) associated therewith. Data is transferred from the bit lines of the associated array through a transfer gate (90) for storage in the shift register (86). A tap latch (88) is provided on the output of each of the shift bits in the shift register (86) for determining the output therefrom. The tap latch (88) stores a tap decode signal which is decoded from a tap address by the column decoder (30). The column decoder (30) also decodes the column address in the random mode. The tap decode signal selects any of the shift bits in the shift register (86).

Abstract: A voltage comparator for an analog to digital converter is provided which includes several differential amplifier stages connected in cascade that determine the existence of a voltage difference between the two input signals and amplify this voltage difference successively. The comparator further includes offset correction voltage circuits which are connected to each differential amplifier stage and allow for the correction of errors caused by the mismatching of the devices internal to each of the differntial amplifier stages.

Abstract: In a video computer system, an improved memory circuit is provided which is effective for delivering stored data only at appropriate instances, and which is also simpler and more reliable in design. In particular, the system preferably includes a bit-mapped RAM circuit which assumes a serial mode in response to both a row address signal and a suitable data output control signal, and which assumes a parallel or "random" mode when only the row address is received. Stored data is transferred to a parallel output terminal in the RAM circuit, or to a serial output terminal therein, depending upon the sequence of these signals as well as the column address and read signals, whereby the data output control signal is used for two separate and different purposes within the system.

Abstract: A video system includes a processor, CRT monitor, video memory and a video memory and CRT controller that provides rapid transfer of data to be displayed in both the text and graphics mode.

Abstract: A generator circuit for producing a negative bias voltage on a substrate for a semiconductor device employs a multistage on-chip oscillator driving individul charge pump circuits for each stage. The oscillator may produce a frequency related to the value of the negative bias, using a feedback circuit. Each of the charge pump circuits includes a capacitor and an MOS diode coupled to the substrate and another diode coupled to the ground terminal of the supply.

Abstract: A video memory controller controls a DRAM (dynamic random access memory) used as a video memory and as a system memory. The video memory and the video memory controller are normally a part of a video system which includes a data processor, the video memory, the video memory controller, a CRT controller and a CRT display device. The video memory controller includes a row address latch for storing a row address from the data processor, a column address latch for storing a column address from the data processor, a refresh address register for storing a memory refresh address and a display update generator for sequentially generating the addresses necessary for update of the CRT display. A multiplexer couples the proper address to the video memory under control of a memory cycle generator which generates the timing of the memory refresh and display update. An arbiter device enables only one of the possible memory cycles at a time.

Abstract: A video system has a processor processing of data to be displayed on a CRT monitor. A memory which is the embodiment shown is a multiport dynamic random accessed memory, stores the data therein according to X and Y coordinates. A video controller controls the transfer of data between the processor and the memory; the controller also, has included therein an X and Y address logic for providing the X and Y coordinates to the memory.

Abstract: A mounting substrate (10) is formed from a platelet of graphite (22) conformally coated with a layer of silicon carbide (24). A layer of silicon dioxide (25) is disposed thereon and a chip (16) mounted onto the substrate (10). The silicon carbide has a thermal expansion coefficient that is essentially equal to silicon in addition to a high thermal conductivity.