Abstract: A method for etching titanium nitride local interconnects is disclosed. A layer of titanium nitride is formed as a by-product of the formation of titanium silicide by direct reaction; this layer of titanium nitride is present over the titanium silicide layer, as well as over insulators such as oxide. A plasma etch using CCl.sub.4 as the etchant is used to etch the titanium nitride anisotropically, and selectively relative to the titanium silicide due to the passivation of the titanium silicide surface by the carbon atoms of the CCl.sub.4. Excess chlorine concentration may be reduced, further reducing the undesired etching of the titanium silicide, by providing a consumable power electrode, or by introducing chlorine scavenger gases into the reactor. The plasma may be ignited by exposing the gases to a mercury/argon light source, photodetaching electrons from the anions in the gas.

Abstract: A process for forming shallow silicided junctions includes the step of sputtering a layer of titanium (28) over a moat region to cover a gate electrode (18) and a sidewall oxide (22) formed on the sidewalls of the gate electrode (18). The titanium is reacted with exposed silicon regions (24) and (26) to form silicide layers (30) and (32) and then dopant impurities are implanted into the substrate (10) prior to stripping the unreacted titanium. The unreacted titanium (36), (38), or (40) functions as a mask to both offset the implanted regions from the channel region (20) under the gate electrode (18) and also to prevent impurities from entering the substrate at regions outside the defined moat region.

Abstract: One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention.) A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N+ layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.

Abstract: A method and apparatus is provided for removing submicron sized particles from the surface of a silicon semiconductor wafer (38). Conventional cleaning methods are capable of only removing particles that are about 1 micron or larger in size. The present invention provides a way to increase the submicron particles in size so that they are removable by the known methods. The silicon semiconductor wafer (38) is cooled by a refrigeration unit (36) or by exposure to liquid nitrogen (74). The cooled wafer (38) is then exposed to a condensable material (42) which is allowed to condense on the surface of the wafer (38). The condensable material will surround any particles that are on the surface and cause them to grow in size due to the formation of frozen crystals. Without allowing the crystals to melt, the enlarged particles then are removed by any of the known methods.

Abstract: A method for forming CMOS device wherein the NMOS devices are bulk devices and the PMOS devices are SOI devices. The PMOS devices are formed with their channel regions in a silicon-on-insulator layer, preferably a laterally recrystallized annealed-polysilicon layer over a silicon dioxide layer.

Abstract: A method for forming a BICMOS device having MOS devices and bipolar devices formed during the same process includes the step of first forming bipolar MOS regions and then forming gate electrodes in the MOS regions and poly emitters in the bipolar regions. The gate electrodes and bipolar regions have a layer of refractory metal formed on the upper surface thereof and covered by a protective cap. The extrinsic bases formed on either side of the emitter electrode and the source/drain regions are formed on either side of the gate electrode by forming a layer of silicide and implanting the layer of silicide with p-type impurities which are subsequently driven downward into the substrate. The protective cap prevents the p-type impurities from being introduced into the poly emitter.

Abstract: The present invention relates to a bilayer photoresist process, wherein a first planarizing resist layer is applied to a base and a second or top photoresist layer is applied over the first. The top layer resist is sensitive to deep UV light, while the planarizing layer resist is sensitive to near UV or violet light. The top layer, by use of a dye or other means, is opaque to predetermined near UV or violet wavelengths by which the planarizing layer is illuminated. The top layer is patterned using deep UV light. A flood exposure of the predetermined near UV or violet wavelengths is then used to transfer the pattern of the top layer to the bottom planarizing resist layer. Improved resolution is achieved by the use of deep UV light for patterning the top layer. Less costly yet faster illumination of the planarizing layer is accomplished by using near UV or violet light. Additionally pattern degradation due to spurious reflections normally occurring from near UV exposure of the top layer is avoided.

Abstract: A non-volatile memory wherein the channel of the floating gate memory devices is recessed.

Abstract: A non-volatile memory device formed on a face of a semiconductor substrate which includes an array of electrically programmable read only memory cells, a Y address decoder coupled to said array and first and second sets of input/output lines coupled to said Y address decoder. Switch means isolates either the first or second set of input/output lines from the Y decoder. A programmable non-volatile memory element is coupled to programming ones of the input lines and is programmable into a programmed state from an unprogrammed state in response to a programming voltage applied to programming ones of the first set of input lines. A control circuit is coupled to the switch means and to the memory element for isolating the first or second set in response to an external signal applied to a selecting one of the first set of input/output lines and in response to the state of the non-volatile memory element.

Abstract: A polyphase parity generator circuit for generating parity of multiple bit data values on a data bus during one or more phases of a bus cycle. The circuit includes a prestage circuit having a plurality of parallel decode circuits couplable to respective pairs of input data lines. Each decode circuit has an odd and even output line for providing output signals in response to odd or even number of 1's (or 0's) on an associated pair of row lines, respectively. The circuit includes a precharge discharge circuit coupled to the prestage circuit for generating a first parity signal in response to an odd number of 1's being on the input data lines and a second parity signal in response to an even number of 1's being on the input data lines.

Abstract: A CMOS device wherein the NMOS devices are bulk devices and the PMOS devices are SOI devices. The PMOS devices are formed with their channel regions in a silicon-on-insulator layer, preferably a laterally recrystallized annealed-polysilicon layer over a silicon dioxide layer.

Abstract: A graphics data processing apparatus having graphic image operations on two images. Two graphic images are formed into a single combined image based upon a predetermined combination of the multibit color codes representing corresponding pixels of the two images. A transparent color code is permitted for the first of the graphic images. The combination of a transparent color code from the first graphic image with any color code from the second graphic image yields the color code of the second graphic image. This innovation enables the use of color codes having selectable numbers of bits set by the number stored in a pixel size register. In particular the transparent color code, which is detected by a transparent color code detection device independent of the image operation, has a selectable number of bits set by the pixel size register in a manner like any other color code.

Abstract: A semiconductor device is programmed by a laser beam which causes an insulator between two conductors on a silicon substrate to be permanently altered, as by breakdown of the insulator. The conductors may be metals such as aluminum or tungsten, and the insulator is a layer of deposited or thermal silicon oxide. The breakdown may be enhanced by voltage applied between the conductors while the laser beam is focused on the structure.

Abstract: An electrically programmable read only memory device formed in a face of a semiconductor substrate of a first conductivity type which includes a pair of spaced apart thick oxide isolation regions defining an elongated channel of the substrate therebetween. A floating gate of conductive material overlies a portion of one of the isolation regions and a first portion of the elongated channel being separated from the oxide isolation and channel regions by an insulator layer. A control layer of conductive material extends over the channel and the floating gate separated from both of the latter by an insulator layer. Buried diffused regions are located below each oxide isolation region.

Abstract: The disclosure relates to a method for reducing filament formation over the BN+ oxide in semiconductor devices wherein a sidewall oxide is formed on the side walls of the first polysilicon layer prior to subsequent formation of the intermediate insulating layer, formation of a second polysilicon layer and subsequent anisotropic etch to provide for removal of all polysilicon over the field oxide.

Abstract: A local interconnect system for VLSI integrated circuits. After titanium is deposited for self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a hardmask is deposited and patterned over the titanium. When a conductive titanium nitride layer is formed overall, it will already be patterned according to this hardmask.

Abstract: In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, column address to the RAM unit is also used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the shift register containing only the data bits of interest.

Abstract: Erasable programmable memory cell having a control gate, a row line and bit line is disclosed. Line driving circuitry coupled to the bit line and control gate applies a negative voltage to the bit line during the ERASE mode. The latter voltage is such that the voltage across the control gate, floating gate and drain of the floating gate transistor is sufficiently great to cause charging of the floating gate. The construction of the line driving circuit for applying the various voltages, including the negative erase voltage, to the control gate of the floating gate transistor is also disclosed. The line driving circuit is responsive to a control signal indicating the operating mode of the memory, and further includes blocking transistors so that the V.sub.pp voltage of the write operation is not coupled back to the circuit input which receives the control signal.

Abstract: One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer, and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention). A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N+ layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.

Abstract: A method of making an array of programmable read only semiconductor memory cells which includes forming an extra row of the memory cells and a corresponding extra row gate coupled thereto. Extra row gate enabling means is coupled to the extra row gate for enabling the extra row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to the control signal KILLT being applied thereto.An NAND gate may be formed with the extra row gate to allow a second set of signals corresponding to a second selected row of memory cells to enable the second selected row gate. A disabling means is coupled to the second selected row gate other than the extra row gate.