Abstract: An interrupting node for providing interrupt requests to a pended bus. The interrupting node provides to the pended bus an interrupt request message including ID data for identifying the interrupting node as the source of an interrupt request. An interrupt servicing node provides interrupt acknowledge messages including destination data specifying a particular interrupting node at times when the interrupt servicing node is ready to service an interrupt request message. The interrupting node detects whether an interrupt acknowledge message on the bus includes destination data specifying that interrupting node, and provides an interrupt vector message to the bus in response.

Abstract: There is provided a mechanism for propagating exception conditions in a computer system when instructions are subject to exception conditions. The apparatus includes a set of data registers for storing data manipulated by the instructions of the computer system, and a set of state registers for storing speculative states of data manipulated by the instructions, there being one state register associated with each data register. Furthermore, the apparatus includes a logic circuit, coupled to the set of state registers, for propagating the states from a source one of the state registers to a destination one of the state registers, if data stored in an associated source one of the data registers are used as a source for an associated destination one of data registers, and if data stored in the source data register were manipulated by a particular instruction subject to an exception condition.

Abstract: An apparatus and method for dynamically tuning queue depths to provide improved storage subsystem throughput and resource utilization across a full range of I/O loads is described. The maximum allowable queue depth for a command queue is adjusted at predetermined cycle intervals on the basis of an I/O workload measured during the cycle. In one embodiment of the invention, the interval is a fixed system parameter, but in an alternative embodiment, the interval size is automatically adjusted to keep the rate of adjustment of the maximum allowable queue depth within a preferred range. In a preferred embodiment, the size of each I/O command is stored before it is sent to the device queue. Read, write and miscellaneous I/O commands may be queued and managed separately. After a predetermined number of commands have been stored, the predominant command size during the cycle interval is determined.

Abstract: An interactive video system employs Motion Picture Expert Group (MPEG) video compression to transfer images from a remote server to a television. The images correspond to dialog frames in a graphical user interface. During an authoring process, the dialog frames are created by first creating a background image and then adding foreground elements, such as buttons. A set of MPEG video frames is created by encoding the resulting images according to the MPEG algorithm. The MPEG video frames are delivered to the television in sequence, where an MPEG decoder uses them to reconstruct the dialog images that are subsequently displayed. The system also contains an object-oriented database that maintains the necessary MPEG file ordering and also carries out menu navigation commands received from the user. The object classes include NODE, BRANCH, and DISPLAY. NODE objects correspond to dialog frames, and BRANCH objects correspond to user-selectable features such as buttons.

Abstract: An apparatus for enforcing that selected instructions are executed in a correct order, comprising a first content addressable memory for storing load addresses of data read from the memory by the selected instructions. The first content addressable memory comparing the store addresses with the load addresses of data to be written to the memory. The first content addressable memory generating a first signal, if one of the load addresses is identical to a subsequently compared one of the store addresses. The apparatus further including a second content addressable memory for storing and comparing states of the data read and written by the selected instructions. The second content addressable memory generating a second signal, if one of the stored states is identical to one of said compared states. The stored states including a program counter to repeat the execution of the selected instructions upon detecting the first and second signals.

Abstract: A compiler groups instructions into sets. The sets of instructions are related by data and control dependencies which are unresolvable by the compiler. Sets of instructions having unresolved dependencies are executed in a speculative state of the computer system under the assumption that an exception condition will not occur. However, if an exception condition does occur while executing a set of instructions in the speculative state, that exception condition is detected and the set of instructions is re-executed in a real state of the computer system to resolve the exception condition.

Abstract: An equipment cabinet employs a rack-mountable equipment enclosure surrounded by a base, a cap, and front and rear covers. Each cover consists of a bezel and a door reversibly mounted thereon via removable hinge pins. The bezels have sidewalls that rest against ledges on the edges of the enclosure to receive support therefrom. The door has a centrally-located latch, the latch having a pawl with an eccentric catch portion that engages a latch opening on a ledge extending from the bezel. The pawl also has a tab that rests between the ends of an arcuate raised portion on the rear of the door to limit the rotational travel of the pawl.

Abstract: A clipping circuit and method for selecting a rectangular region of interest from an image comprised of scan lines of pixels. The circuit stores the lengths of the portions of scan lines inside and outside the region of interest. A data decompression unit presents image data to the clipping circuit in scan line order. When pixels from the portion of a scan line within the region of interest are processed, the circuit passes the pixels through the system. When pixels outside the region are processed, they are blocked from further processing by the circuit.

Abstract: The present invention is a method and an apparatus for the precise quantitative measurement of the magnitude of force exerted at the points of contact on a high density electrical interconnect that quantitatively determines the magnitude of the force. The invention includes the steps of establishing a pressing relationship between a photoelastic material and the high density interconnect, coupling plane-polarized light into the photoelastic material stressed as a result of the pressing relationship with the high density interconnect, coupling of the polarized light being at 45 degrees with the direction of pressing, capturing an image of the fringe pattern of the plane polarized light exiting the stressed photoelastic material, the fringe pattern comprising of fringes wherein the number of fringes varies with the magnitude of the pressing force, and counting the number of fringes produced to determine the magnitude of force exerted on the photoelastic member.

Abstract: A memory controller having a non-volatile memory is disclosed herein. The memory controller forms part of a computer system that includes a program for accessing the non-volatile memory. When memory errors are detected, data correlative to the detected memory errors, such as error syndromes, is stored in the non-volatile memory. Preferably, during each operating session, the area of the non-volatile memory designated for this type of storage is copied into volatile memory. The volatile memory is updated during the operating session and then copied back to the non-volatile memory when the operating session is terminated. Technicians may access the non-volatile memory to study the error history for diagnostic or design purposes.

Abstract: A method and apparatus for providing asynchronous communication between at least one central processing unit (CPU) and at least one associated memory unit with specially programmed timing signals to latch, select and transmit data between them.

Abstract: Threshold optimization for SOI transistors is achieved through the formation of a layer of positive charge within the gate to correspond to the positive polarity formed in the substrate by ion implantation for threshold voltage control. A positive charge layer is formed by furnishing sulfur ions on the substrate before growth of an oxide to form a portion of the gate oxide. The sulfur will form a charge layer on the surface of the oxide, and an additional oxide is then deposited on the same to form the gate oxide as a sandwich with the positive charge layer in the same.

Abstract: A portable computer enclosure with a bumper rail on the sidewalls, the rail being of such width in relation to the height of the sidewalls and being of such height above the surface of the sidewalls that the rail is effective to provide bump protection to the sidewall. The portable computer enclosure with the bumper rail is built to withstand bumping and accidental latch releases, thereby protecting the computer.

Abstract: A pedestal assembly having two opposing and abutting parts, each including a base portion, a wall, both a locking extension and a locking recess, such that the two parts interlock to create a floor region for holding a computer enclosure.

Abstract: This disclosure describes an Interconnect Stress Testing (IST) system and a printed wiring board test coupon which is used with the IST system. The system includes a computer device and a cabinet which is used for mounting the test coupon as well as housing a number of the other components that make up the system. During a pre-cycling phase, the system determines the correct current that should be passed through the coupon in order to heat it to a predetermined temperature. After that test current value is determined the system actually stress tests the coupon by passing the determined test current through the coupon. It does so for a selected number of cycles, and monitors resistance changes in the coupon during testing while recording test data. This disclosure also describes the test coupon, which is designed to uniformly dissipate the heat created during stress cycling.

Abstract: In a storage system having a plurality of disks arranged in a RAID-4 or RAID-5 array, a method of improving the performance and reliability of the array in the absence of a member. The method re-organizes the array into the equivalent of a higher performance and reliability RAID-0 organization while allowing concurrent high performance application access to the array and includes a deliberate reorganization activity concurrent with application access. The method also restores the RAID-4 or RAID-5 organization subsequent to the failure of a member using a replacement member while continuing to allow concurrent high performance application access to the array. In order to perform this reorganization on-line state information is maintained for each parity block, each data block and the array itself. A recently removed disk may be reinserted using an expedited replacement process.

Abstract: A key switch and resilient actuator assembly that includes an electrical switching region and a hollow open ended actuator cover of elastomeric material overlaying the switching region with the open end of the actuator cover in surrounding relationship with the switching region. The actuator cover includes a first wall portion shaped to provide substantially linear resistive force during compression displacement of the cover toward the switching region and to provide substantially linear restoring force during expansion displacement of the actuator cover away from the switching region. The actuator cover further includes a second wall portion shaped to undergo buckling toward the switching region at a predetermined compression displacement and to undergo unbuckling away from the switching region at a predetermined expansion displacement that is smaller in total displacement than the predetermined compression displacement.

Abstract: In a network adapter for a host computer, the data occupancy level of a buffer memory used to store network packets is monitored, and the occupancy level is reported to the host. The buffer memory is organized as a plurality of fixed-size pages. A memory controller uses an allocation counter to track the number of pages available to store incoming data packets, and the value of the allocation counter is compared with a programmable threshold. A data word accompanies each packet delivered to the host to indicate whether the allocation count exceeds the threshold. When the buffer memory has insufficient free space to store an incoming packet, the packet is discarded. The network adapter keeps a count of the number of discarded packets. An adapter manager microprocessor, which is part of the network adapter, reports the count to the host computer on request. The adapter manager also reports the value of the allocation count and other important network adapter variables to the host computer.

Abstract: Threshold optimization for SOI transistors is achieved through the formation of a layer of charge within the gate oxide, which layer has a polarity corresponding to that of the ion implantation for threshold voltage control. A negative charge layer is formed by furnishing trace amounts of aluminum on the substrate before growth of an oxide to form a portion of the gate oxide. The aluminum will form a charge layer on the surface of the oxide and an additional oxide is then deposited on the same to form the gate oxide as a sandwich with the charge layer in the same.

Abstract: A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in memory accesses used to fill the stream buffer. The system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. The system also prevents the unnecessary prefetching of data by preventing certain CPU requests from being used to detect streams. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access.