Abstract: A remote delay regulator circuit measures the effects of intrinsic propagation delays experienced by a system clock signal propagating through an extended clock distribution path that encompasses a clock repeater chip, a module transmission network and a clock distribution network of an integrated circuit (IC) chip. Delay measurement of the associated (IC) chips on the module is provided by sensing the clock signal at the beginning of the network and at the end of the network. The BEFORE and AFTER sense taps are routed to a signal generation circuit on the repeater chip where measurement signals are generated that define the beginning and end of a measurement cycle. A clock delay path circuit on the repeater chip contains the logic circuitry required to measure and compensate for the actual measured intrinsic propagation delays of the total clock transmission network.

Abstract: An electronic testing system can test an electronic device which has more signal pins or pads (i.e., contacts) than the maximum number of tester probes. The testing system connects the contacts to the tester such that groups of contacts share individual tester signal lines. The testing system uses special selector logic on the device to be tested to determine which particular contacts of the groups are "currently output active", or capable of transmitting data. At each step in the testing procedure, the system can vary the sets of contacts which are chosen to be currently output active, thereby resulting in a high percentage of the possible states of the device being tested.

Abstract: This disclosure describes an Interconnect Stress Testing (IST) system and a printed wiring board test coupon which is used with the IST system. The system includes a computer device and a cabinet which is used for mounting the test coupon as well as housing a number of the other components that make up the system. During a pre-cycling phase, the system determines the correct current that should be passed through the coupon in order to heat it to a predetermined temperature. After that test current value is determined the system actually stress tests the coupon by passing the determined test current through the coupon. It does so for a selected number of cycles, and monitors resistance changes in the coupon during testing while recording test data. This disclosure also describes the test coupon, which is designed to uniformly dissipate the heat created during stress cycling.

Abstract: A cross polarized electromagnetic interference shield apparatus for an electronic device having a Faraday cage made of two sets of planar conductive plates. Each of the two sets of planar conductive plates have parallel aligned elongated apertures which are not aligned in the same direction, and are spaced apart at a predetermined distance. This arrangement provides improved EMI attenuation and improved air flow over prior planar EMI shields, at a lower cost than prior honeycomb shields.

Abstract: An architecture, module set and platform to provide total power protection from utility disturbances. Power supplies employing the invention are built on power buses for utility AC input, battery DC input and conditioned AC output housed in the platform and employ modular line-to-AC-or-DC power-factor-correcting converters and battery/charger sets either housed in the platform or integrated as part of the front end power supply for a critical load such as a computer.

Abstract: Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the logic design being subject to resistive conflicts and to charge sharing, the simulation code including data structures associated with circuit modules and nodes interconnecting the circuit modules. A three-state version of simulation code is generated for the circuit design, the three states corresponding to states 0, 1, or X, where X represents an undefined state. A preanalysis was performed of the three-state version and phase waveforms are stored each representing values occurring at a node of the code. For each phase of a module for which no event-based evaluation need be performed, an appropriate response to an event occurring with respect to the module of the three-state version is determined and stored.

Abstract: A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

Abstract: An apparatus which provides a means of ensuring command synchronization for computer systems employing sliced gate array processors includes a computer bus, a plurality of central processing units and a plurality of input/output processors coupled to the computer bus. Each input/output processor includes means to receive commands from said central processing units. The apparatus further includes means within each of the input/output processors for generating a signal indicating the type of command received from the central processing units and means for receiving from every other input/output processor the command type signal generated by every other input/output processor. In addition, the apparatus further includes means for comparing said command type signals and generating an error signal when the comparison indicates that all of the input/output processors have not received the same command.

Abstract: A method for atomically updating Error Detection Code (EDC) protected data in memory such that the EDC protection is maintained to the granularity of a single microprocessor machine instruction. The method is employed in a memory system having a volatile storage area and at least one nonvolatile storage area, each of the storage areas storing a copy of the protected data and two copies of its associated error detection code. The volatile and nonvolatile storage areas each have a first storage location for storing one of the copies of the associated error code and a second storage location for storing the other of the copies of the associated error code. In such a system, a chosen field with the data structure in the volatile copy is updated. Once the volatile copy is updated, a new error detection code is computed with the data in the volatile copy. The new error detection code is then written to the first storage location in each of the storage areas, volatile and nonvolatile, one at a time.

Abstract: A computer system embodies a first hardware (X) architecture for providing an X domain for an X code. The computer system includes a system for simulating a second hardware (Y) architecture providing a Y domain for Y code and for executing the Y code, and a debugger operable in the Y domain for debugging the X and Y codes. The simulating system includes a sub-system for providing support services for the debugger to enable it to debug the Y code, including modification of Y machine state and setting of breakpoints. The computer system also includes a sub-system for generating a call for cross-domain memory data access under predetermined conditions, such as direct memory access failures.

Abstract: A system and method for providing multiscript aliasing of, and access to name entries in a directory information tree (DIT) stored in one or more Directory Service Agent (DSA) servers, such as in a distributed DIT. Where DIT original entry objects are expressed in a first script, the system provides aliases of the entry objects names in at least one alternative script. An alias object is generated using the alternative-script version of the entry, and is provided with a pointer to the original entry object. A request such as a search or look-up using the alias object, i.e. using the name as expressed in the alternative script, will be reformulated into a request using the original entry object, i.e. using the name as expressed in the original script. Another pointer is provided from the original entry object back to each such alias object. When the original entry object is to be deleted, the system first searches for all aliases of the entry object, by using the pointer(s).

Abstract: A cache memory system and method for selectively removing stale "aliased" entries, which arise when portions of several address spaces are mapped into a single region of real memory, from a virtually addressed cache, are described. The cache memory system includes a central processor unit (CPU) and a first-level cache on an integrated circuit chip. The CPU receives tag and data information from the first level cache via virtual address lines and data lines respectively. An off-chip second level cache is additionally coupled to provide data to the data lines. The CPU is coupled to a translation lookaside buffer (TLB) via the virtual address lines, while the second level cache is coupled to the TLB via physical address lines. The first and second level caches each comprise a plurality of entries. Each of the entries includes a status bit, indicating possible membership in a class of entries that might require flushing.

Abstract: In a distributed interactive multimedia service system, a client application of a set-top box located at a customer premises generates an attach request. A session manager, in response to receiving the attach request via a network, generates an allocation request and a create request. A resource manager, in response to the allocation request, allocates resources of a plurality of multimedia servers. The resources can include processor, memory, disk, and network resources. A media stream manager, in response to the create request, creates a multimedia stream. The session manager, in response to the resources being allocated, and the multimedia stream being created, launches a selected one of a plurality of multimedia services in the plurality of multimedia servers. The selected service provides multimedia information to the set-top box via the multimedia stream.

Abstract: An apparatus and method for performing a skip list insertion sort on a singly linked list of elements is provided. Each element to be sorted includes a key, an element pointer in an element pointer field and a flag bit. Also provided is an indexed array of pointer arrays. If an element is to be inserted at a node level greater than zero, a free pointer array is allocated by storing an index corresponding to the allocated pointer array in the element pointer field and setting the corresponding flag bit. If a free pointer array is not available, then the node level of the element is forced to zero. If the level of the element is either assigned as or forced to zero, the flag bit is not set and the pointer array itself occupies the element pointer field as the element pointer instead of the index. Thus, the pointer to the element pointer field will point directly to the specified pointer array location without having to index into the array of pointer arrays.

Abstract: A high-efficiency apparatus for real time measuring of parameters and operational times of vehicles running around a racetrack. At least one detecting station is arranged at a location along the racetrack and is set up to both receive and transmit radio frequency (RF) signals both from/to a transceiver unit installed on each vehicle, the transmitting from the transceiver unit being in response to the transmitting from the detecting station, the station being provided with an electronic radio frequency-converter for transmitting and modulating the received signals over a wide band coaxial cable.

Abstract: A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. A mechanism for tracking address and command transactions occurring on the bus produces, for each address and command transaction occurring on the address bus, a corresponding sequence number tag. Those sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node are stored by the data bus sequencer. The data bus sequencer further includes circuitry for counting the number of data transactions occurring on the data bus, comparing the counted number of data transactions to the stored sequence number tags and initiating data transactions on the data bus in response to the comparison.

Abstract: A system for assigning addresses to devices interconnected on a small computer system interface (SCSI) bus. A device address bus independent of the SCSI bus interconnects address assignable devices on the SCSI bus. The devices, each of which has a SCSI ID by which it is identified and being set with default bus address information representing the SCSI ID, are connected to one or more address lines on the device address bus. A system user can selectively reconfigure the bus addresses of the devices by utilizing a personality unit to override one or more bits of the bus address information. The personality unit includes a bus address selector, coupled to the device address bus, which selects address lines according to user input. The selecting of an address line effects a change in the default bus address information associated with the one or more devices connected to the selected address line.

Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.

Abstract: A system and technique for optimizing the efficiency of maintenance operations performed on skip lists of data elements or nodes stored in memory is provided. Each node of a skip list includes a back pointer for pointing to an immediate predecessor node and a node level field for recording the node level associated with the node. The system further includes a system agent for operating on the data structure, the system agent capable of locating the address of the immediate predecessor node pointing to a selected node by using the back pointer in the selected node.

Abstract: A read buffering system and method employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter.