Abstract: Switch resources for a one-sided crosspoint switch with distributed control (i.e., switch ports, internal busses and controllers) have been organized so that modular growth is facilitated by: (1) assigning each switch port uniquely to one of the controllers; (2) making each controller handle only the crosspoints connected to the switch ports assigned to it; (3) assigning each internal bus uniquely to one of the controllers; and (4) providing a network for the controllers to communicate with each other.

Abstract: A method and apparatus is disclosed for folding the execution of a multi-way branch or switch based upon an operand (e.g.,the block of instructions normally associated with a case statement) into a single instruction. This insulates branch prediction mechanisms from making incorrect predictions that are normally associated with a multi-way branch. A table saves the past history of multi-way branch execution. This table contains three fields: the starting address of a multi-way branch; a value of the operand used to execute that multi-way branch in the past; and the larger target address generated by that multi-way branch in the past when that particular operand value was used. In accordance with one embodiment of this invention, other branch prediction mechanisms (such as a Branch History Table or Decode History Table) are disabled from redirecting instruction fetching during execution of a multi-way branch in an instruction stream.

Abstract: An apparatus, embodied in an Intelligent Page Store, for providing concurrent and consistent access to a functionally separate transaction entity and a query entity to a shared database, while maintaining a single physical copy of most of the data. The Intelligent Page Store contains shared disk storage, and an intelligent versioning mechanism allows simultaneous access by the transaction entity and the query entity to the shared data. The transaction entity is presented the current data and the query entity is presented a recent and consistent version of the data. A single copy of all but recently updated pages is maintained by the Intelligent Page Store. The query and transaction entities operate independently of each other and are separately optimized.

Abstract: A method for increasing cache concurrency in a multiprocessor system. In a multiprocessor system having a plurality of processors each having a local cache in order to increase concurrency the directory entry for a line in local cache will be assigned an LCH bit for locally changed status. If the last cache to hold the line had made a change to it this bit will be set on. If not, the bit will be off and thereby allow the receiving or requesting cache to make change to the line without requiring a main storage castout.

Abstract: Methods and apparatus are described for processing branch instructions using a history based branch prediction mechanism (such as a branch history table) in combination with a data dependent branch table (DDBT), where the branch instructions can vary in both outcome and test operand location. The novel methods and apparatus are sensitive to branch mispredictions and to operand addresses used by the DDBT, to identify irrelevant DDBT entries. Irrelevant DDBT entries are identified within the prediction mechanism using state bits which, when set, indicate that: (1) a given entry in the prediction mechanism was updated by the DDBT and (2) subsequent to such update a misprediction occurred making further DDBT updates irrelevant. Once a DDBT entry is determined to be irrelevant, it is prevented from updating the prediction mechanism. The invention also provides methods and apparatus for locating and removing irrelevant entries from the DDBT.

Abstract: A method and apparatus for coupled computer systems provides a single network node image when connected to a computer network, so that the network is unaware of the "fine" structure of the computer systems in the machine room. The coupled complex is made available to the network.

Abstract: The performance of some chips (e.g., VLSI processors) may be increased by running the internal circuits at higher clock rates, but use of a higher clock rate is limited by the heat-dissipation ability of the chip's package. Apparatus and a method is described for estimating the total heat accumulated for dissipation at any given time. For the periods that the chip is idle, the clock rate is decreased to reduce heat generation. The heat saved while the chip is idling is available for use later to increase the clock rate above normal, provided that the total heat generated does not exceed the heat-dissipation capacity of the package.

Abstract: A method for allowing weak-searchers of a B+-tree avoid locks that serialize access to the B+-tree structure. The update technique used to achieve this ensures that the B+-tree is always in a correct state on secondary storage so that repair is not necessary after a system failure. The assumption is made that the readers will complete their reading within a specified period but sometimes will need to be restarted because they have not completed their reading within a predetermined time period.

Abstract: In a one-sided crosspoint switch, multiple controllers are used instead of a single controller for control of the switching matrix. The controllers operate in parallel, thereby handling requests for connections and disconnections from ports at a higher speed than with a single controller. In the event of a controller failure, the remaining controllers also take over the control function of the failed controller, thereby providing improved reliability.

Abstract: A cache directory keeps track of which blocks are in the cache, the number of times each block in the cache has been referenced after aging at least a predetermined amount (reference count), and the age of each block since the last reference to that block, for use in determining which of the cache blocks is replaced when there is a cache miss. At least one preselected age boundary threshold is utilized to determine when to adjust the reference count for a given block on a cache hit and to select a cache block for replacement as a function of reference count value and block age.

Abstract: A Fetch-Then-Confirm (FTC) policy is used for the handling of data fetch upon XIEX's in a tightly coupled multiprocessor environment. The fetch and/or use of a requested data line upon XIEX is allowed before the SCE receives the confirmation of validity (or invalidity) of the requested line through the clearing procedure. Whenever a line having uncertain validity is used by a CP the results of execution of instructions depending on the validity of the line should not be committed to the cache until a confirmation is received from the SCE. When the confirmation from the SCE indicates that a line L is known to be valid, all results depending on the validity of L can be processed as usual. If, however, the SCE indicates that a previously fetched line L having uncertain validity is in fact invalid, all operations performed based on L's contents should be aborted and restarted properly when a valid copy of L is received.

Abstract: A method for storing into a non-EX cache line in a multiprocessor system. Upon a store into a non-EX line the instruction execution and the processing of subsequent instructions will continue. The results of the current instruction, however, and any subsequent instruction whose decode and execution depends upon the result of the current instruction or that requires operand fetches, will not be released until the processing of the current instruction is resolved. The request to store into the non-EX line is simultaneously sent to the SCE to obtain the EX state for the line. The SCE serializes storage requests. When a request for EX state is processed, certain XI actions (e.g. XI-invalidates) may be invoked. Any instruction using fetched data XI-invalidated before the resolution of a preceding store at the same CP is considered likely to be invalid, and redone.

Abstract: A modular fail-safe memory and an address generation mechanism that provides load balancing when the memory is shared by a number of processors. A plurality of memory modules are used for the memory with no specific limit on the number of memory modules, and a checksum block is used to back-up corresponding blocks in the other memory modules. The checksum blocks are distributed across the memory modules, and an address generation mechanism determines the checksum location for a specific memory block. This address generation mechanism ensures that checksum blocks are equally divided between the memory modules so that there is no memory bottleneck, is easy to implement in hardware, and is extended to provide similar properties when a module failure occurs.

Abstract: A computer memory management method for cache memory uses a deconfirmation technique to provide a simple sequential prefetching algorithm. Access sequentially is predicted based on simple histories. Each memory line in cache memory is associated with a bit in an S-vector, which is called the S-bit for the line. When the S-bit is on, sequentiality is predicted meaning that the sequentially next line is regarded as a good candidate for prefetching, if that line is not already in the cache memory. The key to the operation of the memory management method is the manipulation (turning on and off) the S-bits.

Abstract: A data cache in a computer operating system that dynamically adapts its size in response to competing demands for processor storage, and exploits the storage cooperatively with other operating system components. An arbiter is used to determine the appropriate size of the cache based upon competing demands for memory. The arbiter is entered cyclically and samples user's wait states. The arbiter then makes a decision to decrease or increase the size of the cache in accordance with predetermined parameters.

Abstract: Apparatus for fetching instructions in a computing system. A broadband branch history table is organized by cache line. The broadband branch history table determines from the history of branches the next cache line to be referenced and uses that information for prefetching lines into the cache.

Abstract: A memory system backup for use in a tightly or loosely coupled multiprocessor system. A plurality of primary memory units having substantially the same configuration are backed up by a single memory unit of similiar configuration. The backup memory unit holds the checksum of all data held in all primary memory units. In the event of the failure of one of the primary memory units its contents can be recreated based on the data in the remaining non-failed memory unit and the checksum in the backup unit.

Abstract: An electron sensitive surface is patternized treated to a high resolution pattern of low-energy electrons without any need to do focussing by emitting the low-energy electrons from a pointed electrode and positioning the apex of the pointed electron emitting source suitably close to the surface being treated.

Abstract: A coherent laser beam having a possibly non-uniform spatial intensity distribution is transformed into an incoherent light beam having a substantially uniform spatial intensity distribution by homogenizing the laser beam with a light tunnel (a transparent light passageway having flat internally reflective side surfaces). It has been determined that when the cross-section of the tunnel is a polygon (as preferred) and the sides of the tunnel are all parallel to the axis of the tunnel (as preferred), the laser light at the exit of the light tunnel (or alternatively at any image plane with respect thereto) will have a substantially uniform intensity distribution and will be incoherent only when the aspect ratio of the tunnel (length divided by width) equals or exceeds the contangent of the input beam divergence angle .theta. and whenW.sub.min =L.sub.coh (R+(1+R.sup.2).sup.1/2)>2RL.sub.coh,where W.sub.min is the minimum required width for the light tunnel, L.sub.

Abstract: A switching system comprising a cross-point switch and a Delta network. The two switches are connected in parallel with common port adaptors. When a port desires a specified time reservation to another port, it sends a request message for the specified time over the Delta network to the requested adaptor at which a reservation processor grants a connection for completion at a fixed time in the future. The reservation grant is then returned via the Delta network to the requesting adaptor which, at the fixed time, sets the cross-point connection on the cross-point switch line associated with the requesting adaptor.