Patents Represented by Attorney Ronald P. Rader, Fishman & Grauer Kananen
  • Patent number: 6140213
    Abstract: In a semiconductor wafer according to this invention, an epitaxial layer is formed on the surface of a semiconductor substrate, a second element which is not the same but homologous as a first element constituting the semiconductor substrate is present to have a peak concentration on the semiconductor substrate side rather than the surface, and this peak concentration is 1.times.10.sup.16 atoms/cm.sup.3 or more.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: October 31, 2000
    Assignee: Sony Corporation
    Inventors: Ritsuo Takizawa, Takahisa Kusaka, Takayoshi Higuchi, Hideo Kanbe, Masanori Ohashi
  • Patent number: 6135839
    Abstract: A field emission display having element including a first electrode, and a second electrode laminated to the first electrode through an insulating layer. The first electrode has an opening; the second electrode has a hole of a planar shape corresponding to that of the opening at a position matched with the opening; and the insulating layer has a through-hole continuous to the opening and the hole. An upper edge portion of the hole is formed into a cross-sectional shape having an edge angle in a range of 80 to 100.degree., and at least part of the upper edge portion of the hole is exposed in the through-hole. In this element, electrons are emitted from the second electrode through the upper edge portion of the hole exposed in the through-hole by applying a specific voltage between the first electrode and the second electrode. With this configuration, a distance between the gate electrode and a field emission portion of the cathode electrode can be accurately controlled with a simple structure.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: October 24, 2000
    Assignee: Sony Corporation
    Inventors: Yuichi Iwase, Masami Okita
  • Patent number: 6135860
    Abstract: A fixture for holding a semiconductor chip during a polishing process can be made to also hold the chip while the chip is inspected by a scanning electron microscope. In this manner, the polishing of the chip may be inspected and monitored without removing the chip from the polishing fixture. This allows polishing to be resumed, if necessary, with more precision. This results because the position of the chip with respect to the polishing fixture has not been altered by removing and then resecuring the chip as would be otherwise necessary for microscopic inspection of the chip.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: October 24, 2000
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventor: Victor Tikhonov
  • Patent number: 6132937
    Abstract: Disclosed are a photocurable composition which is developable with an aqueous alkaline solution and such calcined patterns as a conductor pattern, a vitreous dielectric pattern, and a fluorescent pattern which are obtained by the use of the photocurable composition.
    Type: Grant
    Filed: March 10, 1999
    Date of Patent: October 17, 2000
    Assignee: Taiyo Ink Manufacturing Co., Ltd.
    Inventor: Nobuyuki Suzuki
  • Patent number: 6133790
    Abstract: A plurality of amplifiers are connected in cascade to form an in-line predistortion circuit. The amplifiers are unbalanced in that each amplifier stage in the circuit has two DC voltage rails which are independently controlled to provide different, i.e. offset, DC voltage levels to the unbalanced amplifiers. This unbalance in the amplifiers generates predistortion in a signal which can be used to cancel the inherent distortion caused by a non-linear device which subsequently processes or transmits the predistorted signal. Control of the DC voltage offset in at least one of the amplifier stages is necessary to match the predistortion to the inherent distortion being corrected. A tilt circuit can be used in cascade with the plurality of amplifiers (in front of the RF amplifiers) to compensate the amplitude change caused by the unbalanced RF amplifiers. Either side of the DC voltage can be changed in order to correct for either sublinear or superlinear laser diode curves.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: October 17, 2000
    Assignee: Motorola, Inc.
    Inventor: Shutong Zhou
  • Patent number: 6134195
    Abstract: A recording/reproducing apparatus for recording and/or reproducing the information on or from an optical recording medium by illuminating laser light on it using a double-lens type objective lens unit made up of at least a first lens and a second lens. The apparatus includes a light source for radiating laser light, a first lens for converging the laser light radiated from the light source, a second lens arranged between the first lens and the optical recording medium, a detection unit for detecting the sort of the recording medium and a piezoelectric element for causing relative movement between the first and second lenses for varying the distance between the two lenses in the direction along the optical axis. Specifically, the second lens is moved by a movement unit responsive to the results of detection by the detection unit to vary the separation between the first and second lenses.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: October 17, 2000
    Assignee: Sony Corporation
    Inventor: Hiroshi Kawamura
  • Patent number: 6133763
    Abstract: A high impedance circuit capable of operating at a low voltage without narrowing the dynamic range is provided, which includes a first and a second transistors forming differential-pair type circuit, a third and fourth transistors, a pair of collector resistance elements, a resistance element and a pair of current source circuits. The third and the fourth transistors serve as emitter follower circuits which also functions as a DC shift with respect to the differential-pair type circuit, as well as buffer circuits for heightening an input impedance of the first and the second transistors looked from the base side of the third and the fourth transistors. The current flowing in the resistance element is made current-fedback with respect to the resistance elements by the third and the fourth transistors. The input impedance is determined as Z1=V1/i3=(R1.times.R2)/(R1-R2), and when R1=R2, the high impedance circuit becomes infinite impedance.
    Type: Grant
    Filed: September 16, 1998
    Date of Patent: October 17, 2000
    Assignee: Sony Corporation
    Inventors: Atsushi Hirabayashi, Kosuke Fujita, Kenji Komori, Norihiro Murayama
  • Patent number: 6129173
    Abstract: A personal removable mouthpiece can be slipped over the mouthpiece of a voice amplification instrument. An aperture in the removable mouthpiece allows a user to use the voice amplification instrument without the user's mouth coming into contact with the instrument. When a second user begins using the instrument, the removable mouthpiece is replaced thereby preventing the second user from being exposed to any communicable disease of the first user. The removable mouthpiece includes inner and outer annular walls with an annular opening defined therebetween into which the mouthpiece of the voice amplification instrument is inserted. The inner and outer annular walls are connected at bottom ends thereof by a bottom annular wall.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: October 10, 2000
    Inventor: Paula Panton
  • Patent number: 6128352
    Abstract: A receiving apparatus capable of shortening the channel search time comprising a channel selection circuit comprising a channel selection control circuit which sets the oscillation frequency of a local oscillation circuit shifted over the entire area in the frequency bandwidth when a control signal is received and sets the oscillation frequency to a designated frequency when another control signal is received, a mixing circuit which mixes a high frequency signal with a local oscillation signal to convert the same to an intermediate frequency signal, and an AGC which amplifies the intermediate frequency signal at the time of input of the control signal and adjusts the intermediate frequency signal level to a predetermined level at the time of non-input; a discrimination circuit which discriminates each position of the received channel by a digital signal; and a control circuit which outputs the control signal to the channel selection control circuit and the AGC, makes the discrimination circuit discriminate th
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: October 3, 2000
    Assignee: Sony Corporation
    Inventor: Shunji Maeda
  • Patent number: 6126284
    Abstract: A printing device according to the present invention includes a dye tank for containing a powdered vaporizable dye, an entrance section for liquefying the powdered vaporizable dye and a vaporizing section for radiating a laser light beam onto the liquefied dye transported to it by the entrance section for vaporizing the liquefied dye for thermal transcription of the vaporized dye onto a photographic paper. In this manner, printing may be made without employing an ink ribbon or a thermal head and hence the saving in power and the reduction in size and costs of the printing device may be achieved. Besides, the printing time may be shortened, while the size of the printing paper, may be set freely.A photographic paper according to the present invention includes a light absorbing layer between a receptor layer and a photographic paper base.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: October 3, 2000
    Assignee: Sony Corporation
    Inventors: Shuji Sato, Masanori Ogata, Kengo Ito, Hiroyuki Shiota
  • Patent number: 6126511
    Abstract: Disclosed herein is a polishing device including a polishing plate having an upper surface on which a polishing pad is attached, a polishing head having a lower surface opposed to an upper surface of the polishing pad on the polishing plate, for holding a substrate to be polished on the lower surface, and a pressure source for applying a polishing pressure to the polishing head, whereby the substrate held by the polishing head is pressed against the upper surface of the polishing pad under the polishing pressure applied from the pressure source to perform polishing of the substrate. The polishing head is provided with a contact pressure adjusting mechanism capable of adjusting an in-plane contact pressure of the substrate against the upper surface of the polishing pad on the polishing plate at every area of the substrate. Accordingly, the uniformity and the planarity in the plane of the substrate surface to be polished can be improved with a high throughput.
    Type: Grant
    Filed: July 19, 1999
    Date of Patent: October 3, 2000
    Assignee: Sony Corporation
    Inventors: Hideaki Hayakawa, Takatoshi Saito, Yoshiaki Komuro, Shuzo Sato
  • Patent number: 6128202
    Abstract: To prevent damage to the electrical connections between PLC modules and a backplane during seismic and other vibrational disturbances, a bracket is used having two parallel side members attached to the backplane and a lower support bar connected between the side members to support the PLC modules in the vertical direction. An upper support bar may also be provided between the side plates to hold the PLC modules in the bracket and further prevent vertical movement. The upper and lower support bars may also provide vertical members or a rest in contact with the PLC modules and having a high coefficient of friction to prevent lateral movement of the PLC modules with respect to the backplane.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: October 3, 2000
    Assignee: CE Nuclear Power LLC
    Inventors: Raymond R. Senechal, Gary D. Altenhein, Donald D. Zaccara
  • Patent number: 6128229
    Abstract: In a non-volatile semiconductor memory device of a flash type for recording multivalue data into memory cells, a control is made such that a word line voltage is set in accordance with a distribution state of a threshold voltage at the time of verification of data after the writing, a precharge of a bit line is controlled in accordance with data latched in a latch circuit, whether a threshold value of the memory cell exceeds a voltage applied to word line or not is detected depending on whether a current sufficiently flows in the memory cell or not, a state of the latch circuit is specified by a detection output, and when data is sufficiently written, predetermined data is set into the latch circuit. At the time of reading, a control is made so that a word line voltage is set in accordance with the distribution state of the threshold voltage, the state of the latch circuit is specified depending on whether a current sufficiently flows in the memory cell or not, and the read data is set into the latch circuit.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: October 3, 2000
    Assignee: Sony Corporation
    Inventor: Hiromi Nobukata
  • Patent number: 6127776
    Abstract: A method and apparatus for securing a deflection yoke onto a cathode ray tube includes forming pockets having deformable, resilient inner walls along a circumferential surface of the deflection yoke. When the deflection yoke is mounted on the cathode ray tube, the inner walls deform slightly to conform to a contact portion of the cathode ray tube. The position of the deflection yoke with respect to the cathode ray tube it then adjusted into proper alignment. Once the deflection yoke and cathode ray tube are properly aligned, fast curing epoxy is poured into each of the plastic pockets, wedging the deflection yoke permanently into its desired orientation on the cathode ray tube. The pockets can either be integrally formed with the deflection yoke or they can be manufactured and attached to the deflection yoke in a separate operation.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: October 3, 2000
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventor: Basab Bijay Dasgupta
  • Patent number: 6128588
    Abstract: An integrated wafer fab production characterization and scheduling system incorporates a manufacturing execution system with a scheduling system based on simulation. The integrated characterization/scheduling system provides manufacturing with a simulation tool integrated with the manufacturing execution system to evaluate proposed production control logic as a practical alternative to expensive experimentation on actual production system. Furthermore, simulation models are used to create short term dispatch schedules to steer daily manufacturing operations towards planned performance goals. Innovative features include integration of preventive maintenance scheduling, Kanban based WIP control, an integrated time standard database, a, and real time lot move updates.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: October 3, 2000
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventor: Guillermo Rudolfo Chacon
  • Patent number: 6123031
    Abstract: In order to enable a decorative panel of a table, such as that used in fast food restaurants bars etc., to be readily interchanged in accordance with changes in season or game popularity etc., one of the moldings provided about the edge of the table is arranged to be disconnectable from the remainder of the table to expose a side edge of the decorative panel. In some embodiments, the panel is slidably received in grooves which are formed in moldings while in other embodiments the panel is adhered to the surface of the table top using dual-sided tape. When the panel is retained by way of grooves, the removal of the disconnectable molding permits the panel to be slid out and replaced.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: September 26, 2000
    Assignee: Charles Hayman-Chaffey
    Inventor: Charles Hayman-Chaffey
  • Patent number: 6123190
    Abstract: A storage case comprises a case member and a lid member formed integrally with each other. The case member is open at the top and front side thereof. It consists of a bottom plate, lateral walls provided on the bottom plate along opposite lateral sides of the bottom plate, retainers each provided on the inner surface of the lateral wall to be engaged into an engagement cut in a disc cartridge which is to be accommodated into the storage case, and first engagement projections formed on the inner surfaces of the opposite lateral walls.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: September 26, 2000
    Assignee: Sony Corporation
    Inventor: Masaaki Kuboduka
  • Patent number: 6124903
    Abstract: In a liquid crystal display device including a light shielding film, the liquid crystal display device having a structure capable of avoiding a gate line delay is provided. In the liquid crystal display device including a thin film transistor formed on a substrate, a portion of a light shielding film for shielding against incident light from the side of the substrate, except its portion for shielding the pixel transistor, is disposed under an additional capacitance line or between a gate line and the additional capacitance line and at a position avoiding the gate line, so that parasitic capacitance between the film and the gate line is suppressed.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: September 26, 2000
    Assignee: Sony Corporation
    Inventor: Masayuki Iida
  • Patent number: 6124187
    Abstract: In a method of fabricating a semiconductor device having an N.sup.+ -type layer or P.sup.+ -type layer containing an impurity in a concentration of 1.times.10.sup.19 /cm.sup.3 or more, or a semiconductor device having a silicon based gate electrode structure containing an impurity, the final one of heat treatments each exerting an effect to an active state of the impurity is a high rapid thermal anneal, to thereby suppress an increase in resistance of the N.sup.+ -type layer or P.sup.+ -type layer as a diffusion layer or improve depletion of a poly-Si based gate electrode without occurrence of variations in threshold voltage.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: September 26, 2000
    Assignee: Sony Corporation
    Inventor: Masanori Tsukamoto
  • Patent number: 6122009
    Abstract: A CCD bare chip 12 is disposed on a substrate 1. The CCD bare chip 12 converts condensed light by an image forming lens 4 disposed on a holder 2 into an electric signal and outputs an image signal. The image forming lens 4 is disposed on the holder 2. A housing of the holder 2 is a package 2A that has a diaphragm effect for shielding peripheral rays of light and that shield outer light. The package 2A has a circular hole 3 for allowing light emitted from an object to be entered. The holder 2 is disposed on the substrate 1. In such a structure, an image pickup apparatus is accomplished.
    Type: Grant
    Filed: January 3, 1997
    Date of Patent: September 19, 2000
    Assignee: Sony Corporation
    Inventor: Kazuhiko Ueda