Abstract: A fast circuit switching system that establishes a circuit for each packet-sized data communication. Information is conveyed from a number of communications modules in source channels to a number of port controllers and to a network. Information is conveyed from the network to destination channels. Each communications module includes a transmitter that transmits in an associated source channel, circuit setup request signals defining destination channels and also transmits data. Each port controller stores one of a number of status words defining the availability of the destination channels and each of these status words is cycled to each port controller. A port controller responds to one of the circuit setup request signals and to subsequent data, when one of the status words cycled thereto defines as available, a destination channel defined by the circuit setup request signal, by transmitting the circuit setup request signal and the subsequent data to the network.

Abstract: A fast circuit switching system that establishes a circuit for each packet-sized data communication. A time-slot interchanger included in the system network has a sequential access, circulating control memory, the contents of which can be rapidly and frequently changed with minimal impairment of time-slot interchanger throughput. Such changes are effected by controlling the transmission of information concerning established connections, from a control memory output register to a control memory input register and by controlling the transmission of information concerning new connections, to the control memory input register.

Abstract: A bus fault location arrangement for locating the source of a fault condition on a bus connecting a plurality of devices energized by a power supply. When such a fault condition is detected, a bus diagnostic unit included in the arrangement transmits a signal to place a given one of the plurality of devices in a high impedance state. The bus diagnostic unit then transmits a given signal level on the bus. To determine whether the given device is the source of the fault condition, current flow between the device and the power supply is sensed and an error signal is stored when the sensed current exceeds a predetermined magnitude.

Abstract: An arrangement for the solderless mounting of an integrated circuit chip carrier (13) on a printed wiring board (10). A socket (16), cemented to the board, is provided within which a leadless chip carrier (13) is fitted. Featured is a contact interface element (20) which presents an array of electrically conductive annular springs (27) which electrically connect the contact pads (14) of the chip carrier (13) and the contact pads (15) of the printed wiring board (10). The interface element (20) is clamped between the chip carrier (13) and the printed wiring board (10) by means of a compression spring (31) operating on the upper surface of the chip carrier (13).