Abstract: A design structure is provided for a memory module containing an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.

Abstract: A design structure is provided for a memory module containing a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining.

Abstract: A massively parallel nodal computer system periodically collects and broadcasts usage data for an internal communications network. A node sending data over the network makes a global routing determination using the network usage data. Preferably, network usage data comprises an N-bit usage value for each output buffer associated with a network link. An optimum routing is determined by summing the N-bit values associated with each link through which a data packet must pass, and comparing the sums associated with different possible routes.

Abstract: A method to trace a variable or other expression through a computer program is disclosed. A user determines the variable and the conditions upon which activity of the variable will be monitored. As a result of the invention, every time that variable is referenced in a memory operation or other activity by the program and the conditions set forth by the user are satisfied, the state of that variable is saved as a snapshot without interrupting or stopping execution of the program. The snapshots are accumulated in a history table. The history table can be retrieved and the state of the variable in any given snapshot can be restored. Other variables and expressions can be attached to the trigger variable and the states of these other variables at the time of the activity of the trigger variable may also be saved in the snapshot. The method may be incorporated into a program as a tracing device or a program product separate from the logical processing device executing the program.

Abstract: A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.

Abstract: The present invention includes program storing unit 11 for storing a program, parsing/dependence-information generating unit 12 for generating dependence information and a syntax tree for a program, dependence-information storing unit 13 for storing dependence information, syntax-tree storing unit 14 for storing a syntax tree, dependence-information tracking unit 17 for extracting interface information on a program fragment according to specifying-information specifying the program fragment and extracting a part of a program fragment associated with interface information according to selection information for selecting the interface information, and information input/output unit 15 for passing specifying-information and selection information to dependence-information tracking unit 17 and outputting interface information and a part of a program fragment passed from dependence-information tracking unit 17.

Abstract: A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.

Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least two sublayers of oriented carbon nanotubes. A first sublayer is created by growing carbon nanotubes in a first direction parallel to the chip substrate from a catalyst in the presence of a reactant gas flow in the first direction, and a second sublayer is created by growing carbon nanotubes in a second direction parallel to the substrate and different from the first direction from a catalyst in the presence of a reactant gas flow in the second direction. The first and second directions are preferably substantially perpendicular. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal.

Abstract: A program which is linked or bound by reference (referenced program) into one or more other programs supports multiple valid export signatures, each corresponding to a respective version of the referenced program. When a program is built, it records the current signature of each referenced program it is bound to. When subsequently determining whether to rebuild the program, the previously recorded signature of any referenced program is compared with all currently supported signatures of the referenced program, and only if none of the supported signatures matches does the program need to be re-built to ensure compatibility with the referenced program. Preferably, the referenced program is a program library containing supporting procedures, intended to be used by multiple applications programs which are bound to it.

Abstract: A database management system predicts a selectivity for database query conditions requiring a join of records from different tables. The system identifies at least one skewed value in a field specified in the join condition, and constructs, for each skewed value, a set of hypothetical query predicates in which the field specified in the join condition is replaced with a constant equal to the skewed value. The system then predicts the selectivity for the hypothetical predicates, using any appropriate prediction technique. The selectivities of the hypothetical predicates are used to predict a selectivity for the original query.

Abstract: The present invention provides a method and system for performing file recovery in a computer system coupled to a storage subsystem, wherein a data scrubbing process analyzes said storage subsystem for potential or existing storage errors. The method includes: receiving a report from said data scrubbing process describing said errors, including logical block addresses (LBAs) of storage locations containing errors; interacting with a file system created on logical unit numbers (LUN) provided by said storage subsystem in order to identify file information pertaining to the erroneous LBAs; moving the file pertaining to said erroneous LBAs to a different storage location; updating pointers to said file; in case of an unrecoverable, accessing a backup copy of said file from a backup location; if a predetermined degree of error severity is exceeded, creating an additional copy of said file; and updating the pointers to said file managed by the file system, respectively.

Abstract: A computer system includes at least one processor, multiple memory modules embodying a main memory, a communications medium for communicating data between the at least one processor and main memory, and memory access control logic which controls the routing of data and access to memory. The communications medium and memory access control logic are designed to accommodate a heterogenous collection of main memory configurations, in which at least one physical parameter is variable for different configurations. The bits of the memory address are mapped to actual memory locations by assigning fixed bit positions to the most critical physical parameters across multiple different module types, and assigning remaining non-contiguous bit positions to less critical physical parameters. In the preferred embodiment, the computer system employs a distributed memory architecture.

Abstract: A computer system independently maintains states of multiple condition indicators as logical state data, each indicator for a different respective condition and having at least an active and inactive state. Multiple condition indicators share a single human-perceptible physical indicator having at least (N+1) states, where N is the number of condition indicators, the physical indicator states including a state for all conditions inactive, and a respective separate state for each respective condition active. Preferably, the conditions comprise a fault condition and an identify condition, and the physical indicator is a light which is off if neither condition is active, is constant on if the fault condition is active, and is flashing if the identify condition is active.

Abstract: A computer-implemented method, system and computer product including a scheduling manager residing in memory; whereby the scheduling manager dynamically manages access of additional computer resources to be applied to work items of a program based on their valuations relative to the processing costs thereof.

Abstract: An analytical mechanism for a massively parallel computer system automatically analyzes data retrieved from the system, and identifies nodes which exhibit anomalous behavior in comparison to their immediate neighbors. Preferably, anomalous behavior is determined by comparing call-return stack tracebacks for each node, grouping like nodes together, and identifying neighboring nodes which do not themselves belong to the group. A node, not itself in the group, having a large number of neighbors in the group, is a likely locality of error. The analyzer preferably presents this information to the user by sorting the neighbors according to number of adjoining members of the group.

Abstract: A query access plan for executing a database query is dynamically selected from among multiple alternative query access plans based on the availability of computer resources allocated for running the query. Preferably, a first query access plan is generated based on resources then available, and if it is possible to provide additional resources, one or more alternative plans are generated based on the additional resources. If an alternative plan is significantly better than the original plan based on a comparison of query related parameters, the alternative is chosen for executing the query. Additional resources for running the query may be provided from logically partitioned and/or grid environments.

Abstract: A dual-mode memory chip supports a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.

Abstract: A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.

Abstract: A common consolidation management application provides an interface to the multiple different system management software applications and at least one user input console. An adapter in each of the system management software applications supports communication with the consolidation application. A system administrator issues requests to different system management software applications using a common interface provided by the consolidation application. The consolidation application can be installed over an existing complex of computer systems managed by different management applications, without modifying the managed systems or replacing the management applications.