Abstract: A memory management mechanism a nodal having multiple processors in a massively parallel computer system dynamically configures nodal memory on demand. A respective variable-sized subdivision of nodal memory is associated with each processor in the node. A processor may request additional memory, and the other processor(s) may grant or veto the request. If granted, the requested memory is added to the subdivision of the requesting processor. A processor can only access memory within its own subdivision. Preferably, each subdivision contains a daemon which monitors memory usage and generates requests for additional memory.

Abstract: A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.

Abstract: Disclosed is an apparatus, method, and program product that provides atomic, multi-word load support without incurring additional memory utilization. A double-word is atomically loaded without the use of one or more additional fields and without a lock. An invalidity marker is used in connection with a cache miss time to ascertain whether a loaded double-word has been stored and loaded atomically, and is thus, valid.

Abstract: In a first aspect, a first method of providing communication to a user via one of a plurality of network devices is provided. The first method includes the steps of (1) receiving a plurality of communications for the user from one or more of the network devices in a message queue; (2) selecting a network device based on at least one of respective time thresholds and respective priorities associated with the plurality of network devices; and (3) determining whether the selected network device can receive a communication from the message queue based on at least one of a profile associated with the user adapted to define how the user receives the communication on one or more of the network devices and a ruleset adapted to define how the communication is handled based on criteria associated with the communication. Numerous other aspects are provided.

Abstract: A digital device automatically arranges digital images for display in a stack-based arrangement, wherein images are grouped in multiple stacks according to at least one grouping criterion, and the user can scroll over groups of images. Preferably, the digital device automatically selects a mascot image from each group as the top of the corresponding stack. When the images are displayed using a digital display apparatus, the user can scroll through the mascot images only, without reviewing the other images in each stack. When the user finds a mascot image of interest, he may optionally scroll down the images in the stack. Preferably, images are grouped according to power-on session, and mascots are chosen based on user interaction history.

Abstract: A portable electrical device requiring periodic recharging mates with a corresponding charging device by dropping or placing the portable device on or in the charger without pre-alignment by the user. The charger-to-device interface self aligns the portable electrical device in the charger for charging. Preferably, the charger is a bowl-shaped cradle. The portable device sinks to the bottom of the bowl using the force of gravity and thus aligns the contacts for recharging. Optional magnets may provide additional force to guide alignment.

Abstract: A massively parallel computer system contains an inter-nodal communications network of node-to-node links. Nodes vary a choice of routing policy for routing data in the network in a semi-random manner, so that similarly situated packets are not always routed along the same path. Semi-random variation of the routing policy tends to avoid certain local hot spots of network activity, which might otherwise arise using more consistent routing determinations. Preferably, the originating node chooses a routing policy for a packet, and all intermediate nodes in the path route the packet according to that policy. Policies may be rotated on a round-robin basis, selected by generating a random number, or otherwise varied.

Abstract: A massively parallel computer system contains an inter-nodal communications network of node-to-node links. An automated routing strategy routes packets through one or more intermediate nodes of the network to reach a destination. Some packets are constrained to be routed through respective designated transporter nodes, the automated routing strategy determining a path from a respective source node to a respective transporter node, and from a respective transporter node to a respective destination node. Preferably, the source node chooses a routing policy from among multiple possible choices, and that policy is followed by all intermediate nodes. The use of transporter nodes allows greater flexibility in routing.

Abstract: Programming code embedded in an application automatically converts local client data to emulated HTML multi-part form data, without downloading a corresponding form from a web server. The selection of data for conversion is performed programmatically, without the need for interactive user specification of each data item. The emulated HTML multi-part form data is transmitted to a web server as a service request. Preferably, the client application is a configuration utility which generates a record of a computer system configuration, and the server performs the function of configuration verification on configuration data formatted as emulated HTML multi-part form data. The server concurrently maintains a web page which will, on request, download an HTML form corresponding to a system configuration to a web browser, from which a user may specify a system configuration to be verified.

Abstract: A design structure is provided for a slotted ring network, in which a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.

Abstract: A memory module contains a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining.

Abstract: A smart chip protection system contains a unique public/private identity key pair and uses a separate public/private signature key pair. The identity private key is stored in permanent, secure storage such that it can not be read outside the chip. An issuing entity generates a descriptor containing the identity public key, attribute data, and a digital signature. The digital signature is generated by enciphering a derivation of the identity public key and the attribute data with the signature private key known only to the issuer. The authenticity of the descriptor data is verified by decrypting the signature with the signature public key using a known algorithm, and comparing the result to the derivation of the descriptor data. The identity of the object can be verified requesting the smart chip to perform an encryption/decryption operation using its identity private key, and performing the complement using the public key.

Abstract: A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in a hierarchical tree configuration, in which at least some communications from an external source traverse successive levels of the tree to reach memory modules at the lowest level. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a tree configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.

Abstract: A page table mechanism translates virtual addresses to real addresses. In a first aspect, page table entries are contained in equal-sized blocks, the entries within each block corresponding to contiguous pages of virtual address space. Preferably, the common high-order portion of the virtual address is contained in segments distributed among multiple page table entries of the block. In a second aspect, the virtual address indexes a binary tree definitional structure. Decode logic traverses a binary tree defined by the definitional structure by testing selective bits of the virtual address to reach a leaf of the binary tree, which defines the location of data defining the real address.

Abstract: A memory module contains an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.

Abstract: A smart chip protection system contains a unique public/private identity key pair and uses a separate public/private signature key pair. The internally stored identity private key can not be read outside the chip. An issuing entity generates a descriptor containing the identity public key, attribute data, and a digital signature of the two, using a signature private key known only to the issuer. The authenticity of the descriptor is verified by decrypting the signature using the signature public key, and comparing the result to source data. An object's identity can be verified by requesting the smart chip to perform a data transformation using its identity private key, and performing the complement using the public key. An exemplary embodiment is a cellular telephone, in which a service provider verifies identity of the telephone and correct signature as a condition to providing service.

Abstract: A smart chip protection system contains a unique public/private identity key pair and uses a separate public/private signature key pair. The internally stored identity private key can not be read outside the chip. An issuing entity generates a descriptor containing the identity public key, attribute data, and a digital signature of the two, using a signature private key known only to the issuer. The authenticity of the descriptor is verified by decrypting the signature using the signature public key, and comparing the result to source data. An object's identity can be verified by requesting the smart chip to perform a data transformation using its identity private key, and performing the complement using the public key. An exemplary embodiment is a cellular telephone, in which a service provider verifies identity of the telephone and correct signature as a condition to providing service.

Abstract: Disclosed is a controller that includes a curve matching mechanism. The curve matching mechanism employs Fuzzy Logic to compare input curves to standard curves and to thereby characterize the input curves. Also disclosed in an automotive environment for the curve matching mechanism in which a Fuzzy Controller is used to receive time series data (i.e., input curves) and to present the input curves to the curve matching mechanism. The controller then uses the output of the curve matching mechanism to adjust engine function.

Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

Abstract: The present invention relates to a method, a computer program product and a system of adding new static data variables and initialisation routines for these variables as part of a method of replacing a current version of a computer program with a replacement version of the program concurrently with the execution of the program on a computer system. This replacement version consists of new machine code completely replacing the existing version, new static data variables and initialisation routines for these variables. The content of the existing static variables will be preserved during the application of the concurrent patch. The concurrent patch can be revoked and the new static data variables can be removed such that the computer program that was executed before the application of the concurrent patch will be executed again.