Abstract: A ring-ground circuit in a telephone system comprises a control transistor that selectively receives base drive from a microprocessor and that has its emitter connected through a low voltage LED and through the series combination of the base-emitter junction of a switching transistor and its emitter resistor to ground. The LED has a sharp transition in its conduction characteristics when the voltage across it reaches a predetermined value which is a reference voltage. Conduction of the control transistor provides base drive to the switching transistor for causing collector current in the latter to initiate a ground-start condition in a relay coil that is connected to a central office battery voltage. When current in the switching transistor increases to a prescribed value, that is set by the LED reference voltage and the emitter resistor, conduction of the switching transistor is automatically controlled for limiting the maximum value of its collector current.

Abstract: An active current limiter in only the ring side of a telephone circuit has the control branch of a current mirror resistively connected across a supply voltage for establishing the magnitude of loop current in its other branch. A first resistor is also connected between adjacent one sides of the two branches for causing the control voltage and loop current to vary as a function of loop length. Extraneous metallic voltages on the A and B leads are AC coupled to associated inputs of a differential amplifier having its output connected through a second resistor to the one side of the control branch for modulating the loop current provided by the other branch. Opposite sides of the second resistor are fed back to associated input terminals of the amplifier. The amplitude modulated loop current is also fed back to an input of the amplifier for minimizing the affects of induced metallic voltages on the tip and ring lines.

Abstract: In a data transmission system, apparatus for converting a subrate binary data stream into a binary signal at the line transmission rate comprises means for periodically accepting a date byte from the subrate data stream and; means for expanding the data byte by one additional bit by adding a control bit in the first bit position of the accepting means. The apparatus additionally comprises means for recirculating the expanded data byte through the accepting means a predetermined number of times and means for serially reading out bits of the expanded data byte at the line transmission rate.

Abstract: In a floating battery feed circuit, the voice frequency is normally connected on the subscriber loop side of the blocking capacitor which is used to prevent the DC loop current from flowing in the winding of the associated voice frequency transformer. This capacitor adversely offsets the dial pulse signals. An optical isolator is responsive to the answer control signal from a dial pulse originating (DPO) channel unit and provides a control signal to a switching circuit, which connects the voice frequency circuit to the loop during answer periods and disconnects the voice frequency circuit from the loop during dial pulse signaling.

Abstract: Echo cancellers provide echo return loss enhancement by subtracting a replica of the echo signal from the echo returned via the two-wire to four-wire transition. The echo replica is derived from the signal incoming from the far end by signal processing which consists of a convolution and adaptive modeling that is used to model echo paths caused by the imperfections of the two-wire to four-wire transition. An improved echo return loss enhancement (ERLE) is obtained by dynamic range compression of the incoming signal prior to processing and dynamic range extension following processing. The range extension is slaved to a control signal from the ranged compressor, providing proper compensation for the compressed signal, but insuring that processing noise and other extraneous signals have been adversely treated.

Abstract: A data rate converter for use in telecommunications inserts supervisory bits into a data stream to increase the data rate, in one application, from 56 kbps to a standard 64 kbps. A standard 64 kbps PCM telephone channel uses 8-bit words for transmission, whereas 56 kbps occupies only 7 bits of an 8 bit word in such a telephone channel. Supervisory bits are inserted at the exact time when the data channel clock signal and the transmission line clock signal are in phase alignment.

Abstract: A floating battery feed circuit employs a single primary winding, a pulse width control circuit and a peak detector for providing a controlled current to a subscriber loop. The amplitude of the controlled current is determined by the loop resistance. A comparator circuit has one input connected to the output of a peak detector via a breakdown diode. The second comparator input is connected to a reference voltage. When the voltage from the breakdown diode exceeds a predetermined value the comparator provides an 0 output to indicate an on-hook state. For a peak detector output voltage below said predetermined value, the comparator provides a +5 volt output indicating an off-hook state.

Abstract: A D/A converter having a feedback capacitor C1 between the inverting input and output of an operational amplifier A1 having a virtual ground on the inverting input. First switch means is sequentially responsive to binary values of bits of a digital input word for connecting a bus line to either a reference voltage or ground. Second switch means alternately connects opposite sides of a second capacitor C2.dbd.C1 between ground and the bus line for sampling the logic level of a bit, and across C1 for redistributing sampled charge during each bit. The charge on C1 is transferred to a storage capacitor and then reset to zero at the end of each word. In an alternate embodiment, one of a pair of switched capacitors samples the logic level while the other is connected across C1 for redistributing stored charge. In another embodiment, binary weighted capacitors sample the logic levels of bits in pairs and are simultaneously connected across C1 for redistributing charge.

Abstract: A D/A converter having a feedback capacitor C1 between the inverting input and output of an operational amplifier A1 having a virtual ground on the inverting input. First switch means is sequentially responsive to binary values of bits of a digital input word for connecting a bus line to either a reference voltage or ground. Second switch means alternately connects opposite sides of a second capacitor C2=C1 between ground and the bus line for sampling the logic level of a bit, and across C1 for redistributing sampled charge during each bit. The charge on C1 is transferred to a storage capacitor and then reset to zero at the end of each word. In an alternate embodiment, one of a pair of switched capacitors samples the logic level while the other is connected across C1 for redistributing stored charge. In another embodiment, binary weighted capacitors sample the logic levels of bits in pairs and are simultaneously connected across C1 for redistributing charge.

Abstract: An integratable mu-law PCM decoder including only a single operational amplifier having a unit valued feedback capacitor C1, and second and third unit valued switched capacitors C2 and C3. Switch means cyclically connects C2 between ground and either ground or a reference voltage, and across C1 for providing an indication on C2 of the step offset in a prescribed segment; cyclically connects C3 between ground and the reference voltage and across C1 for stepping through segments below the prescribed segments; transfers all of the charge on C2 to C1 for the prescribed segment; and alternately connects opposite sides of C3 to ground and across C1 for segments above the prescribed segment for redistributing charge on the capacitors and producing an analog signal sample on C1. In an alternate embodiment for satisfying the A-law, all charge on C3 is transferred to C1 for only a first segment that is below the prescribed segment.

Abstract: Surge-current that occurs when the pair of input lines of a power supply are energized is limited by connecting the source-to-drain path of an insulated gate FET in series in one input line and connecting its gate to an intermediate node of a voltage divider that is connected across the input lines, with an integrating capacitor connected between the node and one input line for reducing the rate of conduction of the FET. Overvoltage protection is provided by electrically connecting a latch circuit between the node and the one input line, with the FET's gate being electrically connected to the collector of a latch transistor that has its base driven by an overvoltage indication. The series combination of a timing resistor and timing capacitor is connected across the primary conduction path of the FET and the base of a unijunction transistor that has its emitter directly connected to the junction of the resistor and capacitor and AC coupled to the base of the latch transistor.

Abstract: An integrated single-sideband modulator comprises six integrated capacitors C1-C6 and first switch means alternately connecting C1 and C2 as feedback capacitors across a differential input operational amplifier A1. The amplifier has a virtual ground potential on its inverting input terminal for causing it to operate as a voltage source and render the circuit relatively insensitive to parasitic capacitance effects associated with capacitor plates. Second switch means cooperates with A1, C1 and C2 and is responsive to 4-phase clock signals for driving input capacitors C3-C6 so as to convert first and second quadrature-phase input signal voltages into first and second electrical charge flow signals on the inverting input terminal that are a function of products of representations of the first and second voltages in switch state time intervals and associated pulse trains which have a 90.degree. phase difference therebetween and a repetitive pattern such as +1, +1, -1, -1, etc.

Abstract: An integrated single-sideband modulator comprises six integrated capacitors C1-C6 and first switch means alternately connecting C1 and C2 as feedback capacitors across a differential input operational amplifier A1. The amplifier has a virtual ground potential on its inverting input terminal for causing it to operate as a voltage source and render the circuit relatively insensitive to parasitic capacitance effects associated with capacitor plates. Second switch means cooperates with A1, C1 and C2 and is responsive to 4-phase clock signals for driving input capacitors C3-C6 so as to convert first and second quadrature-phase input signal voltages into first and second electrical charge flow signals on the inverting input terminal that are a function of products of representations of the first and second voltages in switch state time intervals and associated pulse trains which have a 90.degree. phase difference therebetween and a repetitive pattern such as +1, +1, -1, -1, etc.

Abstract: An integratable mu-law PCM decoder including only a single operational amplifier having a unit valued feedback capacitor C1, and second and third unit valued switched capacitors C2 and C3. Switch means cyclically connects C2 between ground and either ground or a reference voltage, and across C1 for providing an indication on C2 of the step offset in a prescribed segment; cyclically connects C3 between ground and the reference voltage and across C1 for stepping through segments below the prescribed segments; transfers all of the charge on C2 to C1 for the prescribed segment; and alternately connects opposite sides of C3 to ground and across C1 for segments above the prescribed segment for redistributing charge on the capacitors and producing an analog signal sample on C1. In an alternate embodiment for satisfying the A-law, all charge on C3 is transferred to C1 for only a first segment that is below the prescribed segment.

Abstract: A first embodiment of an integrable switched capacitor modulator comprises a differential input operational amplifier A1 having a virtual ground potential impressed on its inverting input terminal; capacitors C1, C2 and C3; and switch means operative for alternately (1) charging C1 with an input voltage while connecting C2 and C3 in series with A1 and across it, respectively, for causing it to produce an inverted version of the input voltage, and (2) discharging C2 and C3 while connecting the sample of the input voltage on C1 across A1 for causing it to output a non-inverted sample of the input voltage. The modulated output signal from A1 is preferably bandpass filtered to eliminate baseband spectral components fed through A1 when C2 is connected in series with the input terminal thereof.

Abstract: An integrated single-sideband modulator comprises six integrated capacitors C1-C6 and first switch means alternately connecting C1 and C2 as feedback capacitors across a differential input operational amplifier A1. The amplifier has a virtual ground potential on its inverting input terminal for causing it to operate as a voltage source and render the circuit relatively insensitive to parasitic capacitance effects associated with capacitor plates. Second switch means cooperates with A1, C1 and C2 and is responsive to 4-phase clock signals for driving input capacitors C3-C6 so as to convert first and second quadrature-phase input signal voltages into first and second electrical charge flow signals on the inverting input terminal that are a function of products of representations of the first and second voltages in switch state time intervals and associated pulse trains which have a 90.degree. phase difference therebetween and a repetitive pattern such as +1, +1, -1, -1, etc.

Abstract: A log-periodic antenna comprises two arrays of dimensionally tapered radiating elements disposed in the E-plane and each fed by a balanced line consisting of the inner conductors of two coaxial cables. In one embodiment the elements of each array are dipoles and in another embodiment are formed of continuous conductive strips in zig-zag patterns on non-conductive support members. Each array preferably have two sets of elements disposed in planes, respectively, which converge toward the smaller end of the array with vertically aligned radiating elements of each set projecting in opposite directions from the array axis. Periodic gain dropout anomalies across the antenna operating band are eliminated by use of a shielded feed line.

Abstract: An integrated single-sideband modulator comprises six integrated capacitors C1-C6 and first switch means alternately connecting C1 and C2 as feedback capacitors across a differential input operational amplifier A1. The amplifier has a virtual ground potential on its inverting input terminal for causing it to operate as a voltage source and render the circuit relatively insensitive to parasitic capacitance effects associated with capacitor plates. Second switch means cooperates with A1, C1 and C2 and is responsive to 4-phase clock signals for driving input capacitors C3-C6 so as to convert first and second quadrature-phase input signal voltages into first and second electrical charge flow signals on the inverting input terminal that are a function of products of representations of the first and second voltages in switch state time intervals and associated pulse trains which have a 90.degree. phase difference therebetween and a repetitive pattern such as +1, +1, -1, -1, etc.

Abstract: Apparatus for frequency tuning a waveguide cavity comprises a retainer ring and a knob that are threaded onto a plunger in a spaced apart relationship, with the plunger extending into the cavity. Means is provided for preventing rotation of the plunger and for securely rotatably mounting the knob on the cavity. Set screws in threaded holes extending through the knob protrude into blind holes in the ring for mechanically coupling them together. Lightly threading the screws into the blind holes reduces backlash in the threads so that rotation of the knob, and thus the ring, causes smooth and even movement of the plunger in the cavity. Tightening the screws firmly in the blind holes binds the threads on the knob, ring and plunger for preventing further rotation of the knob and movement of the plunger.

Abstract: A pulsed or CW laser is rapidly switched to operate at one or more selectable wavelengths by means of intracavity insertion of beam dispersion and focussing elements and an apertured focal plane mask and shutter assembly. The laser beam has an axis and is dispersed into components or sub-beams having different axes and representing different wavelengths, the sub-beams being focussed to substantially reduced diameters on the focal plane mask at points, respectively, at which apertures are formed. Movable shutters adjacent to the respective apertures control alternate opening of and closing of the apertures and selectively permit the laser to resonate at at least one of a plurality of wavelengths corresponding to that of the sub-beam passing through an open aperture. Mask apertures having very small diameters (<50 microns) and separations are achieved enabling switching between different operating wavelengths in milliseconds.