Abstract: A log-periodic antenna comprises two arrays of dimensionally tapered radiating elements disposed in the E-plane and each fed by a balanced line consisting of the inner conductors of two coaxial cables. In one embodiment the elements of each array are dipoles and in an other embodiment are formed of continuous conductive strips in zig-zag patterns on non-conductive support members. Each array preferably has two sets of elements disposed in planes, respectively, which converge toward the smaller end of the array with vertically aligned radiating elements of each set projecting in opposite directions from the array axis. Periodic gain dropout anomalies across the antenna operating band are at least substantially reduced by use of shielded feed lines. In another embodiment which has particular advantage at HF frequencies, a single array is operated over a ground plane which provides a mirror image thereof.

Abstract: A log-periodic antenna comprises two arrays of dimensionally tapered radiating elements disposed in the E-plane and each fed by a balanced line consisting of the inner conductors of two coaxial cables. In one embodiment the elements of each array are dipoles and in another embodiment are formed of continuous conductive strips in zig-zag patterns on non-conductive support members. Each array preferably has two sets of elements disposed in planes, respectively, which converge toward the smaller end of the array with vertically aligned radiating elements of each set projecting in opposite directions from the array axis. Periodic gain dropout anomalies across the antenna operating band are eliminated by use of a shielded feed line. In another embodiment having advantage in direction finding, the sets of elements of each array are located on associated opposite sides of a right rectangular pyramid. These pyramidal arrays are used in pairs for direction finding.

Abstract: An improved method of manufacturing a printed wiring board having the characteristics of one with a solder mask over bare copper for circuit traces and ground planes. The method includes the step of electroplating a very thin coating of tin-lead over the circuit traces, ground planes, holes and circuit pads prior to selectively coating only the pads and holes with a relatively thick coating of tin-lead solder plate. After removing the plating resist which defines the areas for selective solder coating, the board is chemically etched and then mechanically scrubbed to roughen the surface of and reduce the thickness of the thin solder plate. A solder mask may be applied over circuit traces and ground planes prior to reflowing the thick coating of solder plate. Assembled printed wiring boards may then be wave soldered without wrinkling of the solder mask.

Abstract: Apparatus for preventing a fire in electrical equipment when a relatively constant overvoltage condition appears on an input line comprises a meltable fuse in the line and a surge arrestor connected between the equipment side of the fuse and ground. The surge arrestor is physically located adjacent the fuse for melting the latter and open circuiting the line when the overvoltage condition is present for greater than a net prescribed time interval. In a preferred embodiment, the line adjacent the electrical equipment is a printed conductive line on one side of a circuit board, with the fuse comprising a gap in the printed line that is bridged with a bead of solder. The surge arrester is located under the solder bridge, with one of its leads extending through the board and connected to the printed conductor within the solder bridge.

Abstract: A method of fabricating CMOS integrated circuits including the ordered steps of: depositing a layer of phosphorus doped silicon oxide; heating the oxide layer at a temperature and duration sufficient to reflow and densify it; forming contact apertures in the oxide layer for exposing source and drain regions of transistors; and cleaning the wafer in an etchant solution for rounding off sharp edges on the oxide layer prior to contact metallization. In a preferred embodiment, all steps between forming contact apertures and through metallization are formed at a temperature that is lower than the temperature that will cause flow of the oxide layer.

Abstract: An integratable PCM decoder that is relatively insensitive to parasitic and stray capacitance effects and that requires a total capacitance of only 32 times the normalized capacitance Co of the smallest capacitor thereof. The decoder comprises a source of positive and negative reference voltages; a differential input operational amplifier having its non-inverting input connected to ground; a storage capacitor CO=16Co connected as a feedback capacitor between the inverting input and the output terminals of the amplifier so that they operate as a voltage source; binary weighted capacitors C1=Co, C2=2Co, C3=4Co and C4=8Co; and a second unit weighted capacitor C5=Co. In an a-law decoder, switch means alternately connects one and other sides of ones of C1-C5 (1) between ground and either a.+-.

Abstract: An integratable PCM decoder requiring a total capacitance of only 32 times the normalized capacitance Co of the smallest capacitor thereof. The decoder comprises a source of positive and negative reference voltages, a differential input operational amplifier having its non-inverting input connected to ground, a storage capacitor CO=16Co connected as a feedback capacitor between the inverting input and the output terminals of the amplifier so that they operate as a voltage source, binary weighted capacitors C1=Co, C2=Co, C3=4Co and C4=8Co, and a second unit weighted capacitor C5=Co. In a mu-law decoder, switch means alternately connect one and other sides of ones of C1-C5 (1) between ground and either a.+-.reference voltage or ground, in accordance with the characterizations in a PCM coded digital input word, and (2) across the storage capacitor CO for redistributing charge on the capacitors for each segment of a designated polarity.

Abstract: A D/A converter having a feedback capacitor C1 between the inverting input and output of an operational amplifier A1 having a virtual ground on the inverting input. First switch means is sequentially responsive to binary values of bits of a digital input word for connecting a bus line to either a reference voltage or ground. Second switch means alternately connects opposite sides of a second capacitor C2=C1 between ground and the bus line for sampling the logic level of a bit, and across C1 for redistributing sampled charge during each bit. The charge on C1 is transferred to a storage capacitor and then reset to zero at the end of each word. In an alternate embodiment, one of a pair of switched capacitors samples the logic level while the other is connected across C1 for redistributing stored charge. In another embodiment, binary weighted capacitors sample the logic levels of bits in pairs and are simultaneously connected across C1 for redistributing charge.

Abstract: A switched capacitor N-path filter in which all capacitors that introduce delay in the paths, in that they have memory and are characterized such that the new charge flow into each such capacitor during each commutation cycle depends on the old charge on it from the previous commutation cycle, are replaced with an associated plurality of N-commutating capacitors.

Abstract: DC Saturation effects in the VF transformer of a DPT are reduced or eliminated with apparatus diverting cental office battery loop current away from windings of the transformer when a trunk circuit is seized for an off-hook condition of a calling parties telephone handset. A physically smaller transformer having increased inductance may then be employed for providing increased return loss at low frequencies. The apparatus comprises a current amplifier that is electrically connected across tip and ring lines, with a first switch means in its feedback path, and second switch means for AC coupling a transformer winding to the lines. When the trunk is idle for an on-hook condition of the handset, the amplifier is disabled and the lines are terminated with a large resistance.

Abstract: A resistor and diode means are electrically connected in series between nodes A and B on the base electrodes of first and second transistors of a differential amplifier. These nodes A & B are also connected to a source of temperature-compensated load-sensitive reference voltage and to a tap point, respectively, that senses current in the loop of a carrier-serviced subscriber's telephone set. The base and emitter of a control transistor are also connected to associated nodes A and B. Conduction of the diode means and control transistor prebiases the latter and reduces the reference voltage during an on-hook condition. When the handset goes off-hook, the node B voltage rises faster than that on node A for decreasing the conduction rate of the control transistor to indicate an off-hook condition, and eventually cutting off the control transistor prior to the diode means. This operation of the diode means extends the loop length over which the circuit will detect an off-hook condition.

Abstract: Stacked leaded hybrid substrates and associated carrier plates are exited from a reflow solder operation onto a vibrating table. Vibration of the table sequentially advances each stacked carrier and substrate until components on the latter contact an arm that is spaced above the table. Detection of the presence of a substrate and carrier adjacent the arm causes a plunger to move transversely across the table and into contact with an edge of the substrate. Further movement of the plunger pushes an edge of the carrier into contact with spring loaded pins in the table top. The shear force created on contiguous surfaces of the substrate and carrier by the plunger and pins causes the substrate to slide off of the carrier and over the pins. If this shear force exceeds a prescribed value, the pins rotate into the table top for passing a carrier and/or substrate without damaging the latter.

Abstract: A voltage comparator compares the DC current in active elements of a trunk amplifier with a variable reference voltage for detecting when to switch to a bypass mode. Its output is normally low for passing a current through it, an LED, and relay coils when the amplifier operates satisfactorily.

Abstract: Method and apparatus for aligning one end of an optical fiber in the emitting well of an LED employs an elongated rod having a flat milled halfway through the mid-section thereof for forming a recess and first and second channels extending between the recess and an associated end of the rod to the depth of the recess. The two channels are located in front of the bottom of the recess and are oriented at 90.degree. with respect to each other in an end view. The channels also overlap along the center line of the rod and are dimensioned for loosely-releasably receiving and supporting a length of fiber in a straight line while the one end thereof is aligned with the emitting surface of the LED.

Abstract: Stacked leaded hybrid substrates and associated carrier plates are exited from a reflow solder operation into a vibrating table. Vibration of the table sequentially advances each stacked carrier and substrate until components on the latter contact an arm that is spaced above the table. Detection of the presence of a substrate and carrier adjacent the arm causes a plunger to move transversely across the table and into contact with an edge of the substrate. Further movement of the plunger pushes an edge of the carrier into contact with spring loaded pins in the table top. The shear force created on contiguous surfaces of the substrate and carrier by the plunger and pins causes the substrate to slide off of the carrier and over the pins. If this shear force exceeds a prescribed value, the pins rotate into the table top for passing a carrier and/or substrate without damaging the latter.

Abstract: A method of determining splice loss 10 log (1-P.sub.R /P.sub.O) that is practiced at the location of a splice between one ends of input and output fibers. A reference level P.sub.O of light that is transmitted out of the one end of the input fiber is obtained by inserting it into an integrating cylinder of split block construction, prior to making the splice, and coupling diffuse light in the cylinder to a radiometer. After the ends of the fibers are spliced together, the splice and a significant portion of the adjacent length of output fiber exhibiting substantial leaky mode radiation that is caused by the splice, is located in the cylinder. With light of the reference level in the input fiber being incident on the splice, the radiometer provides an indication P.sub.R of light lost as a result of the splice. The indication P.sub.

Abstract: A circuit for simulating the parallel combination of a floating inductor and capacitor in the bilinear and LDI domains has a pair of nodes receiving an input voltage and connected to input terminals of associated first and second voltage followers. A first capacitor C1 is alternately or periodically connected across the output terminals of the voltage followers for sampling the input voltage, and connected between the output of the second voltage follower and the input terminal of an integrator including a second capacitor C2 which integrates and stores the charge voltage on C1. A third capacitor is periodically connected to the nodes for sampling the input voltage, and connected between the output terminals of the first voltage follower and the integrator for subsequently also sampling and storing the integrated voltage on C2. The sum of the input voltage and the integrated voltage that is stored by C3 is discharged to the new input voltage when C3 is again connected across the nodes.