Patents Represented by Attorney Ryder, Lu, Mazzeo and Konieczny, LLC
  • Patent number: 8337564
    Abstract: A knee replacement prosthesis comprising a femoral component and a tibial component that enable anterior-posterior translation of the femur relative to the tibia and enable the tibia to rotate about its longitudinal axis during flexion of the knee. The femoral component connects to the distal end of a resected femur and includes medial and lateral condyles having distal, articulating surfaces, and a patellar flange having a patellar articulating surface. The tibial component connects to the proximal end of a resected tibia and includes a proximal bearing surface with medial and lateral concavities that articulate with the medial and lateral condyles. The articulating surfaces of the condyles and concavities are defined by sections of toroids.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: December 25, 2012
    Assignee: Maxx Orthopedics, Inc.
    Inventors: Asit Shah, Murali Jasti
  • Patent number: 8333661
    Abstract: A gaming console may provide safety features that may avoid or minimize the probability of a collision between the user of the gaming console and the surrounding objects while the user is playing a game. The gaming console may include body sensors to continuously track and capture images of the full body movement of the user. The gaming console may comprise proximity sensors, which may scan and capture the images of the surrounding objects at regular intervals of time. The gaming console may use the images of the full body movement and the images of the surrounding objects to determine if the user is close to the surrounding objects, which may cause collision with the surrounding objects. If the user is close to the surrounding objects, the gaming console may generate alert signals that may avoid or minimize the probability of collision of the user with the surrounding objects.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: December 18, 2012
    Assignee: Intel Corporation
    Inventor: Choo Boon Ng
  • Patent number: 8307439
    Abstract: In general, in one aspect, an add-in card includes inaccessible memory to store an identity key, wherein the identity key is to enable a secure communication link. The add-in card also includes an isolated execution environment and a machine-accessible medium comprising content. The content when executed by the isolated execution environment causes the isolated execution environment to route secure communications between an on-line application and a remote service provider through the isolated execution environment to provide a secure communication link therebetween, detect on-line application code modifications, detect on-line application process flow modifications, and notify, via the secure communication link, the remote service provider when a modification is detected.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: November 6, 2012
    Assignee: Intel Corporation
    Inventors: Travis T. Schluessler, Stephen D. Goglin, Erik J. Johnson
  • Patent number: 8289341
    Abstract: A texture sampler is implemented using a shader language. The shader compiler is used to compile the texture sampler to a target machine based on sampler state, sampler operation, and other static factors input values provided to the texture sampler. The shaders such as a vertex shader, geometry shader, pixel shader, hull shader, domain shader, and a compute shader may call one or more texture samplers while the shaders are invoked. The one or more texture samplers, which are a piece of software code may generate texture samples from the texture data and provide such texture samples to the shaders. The shaders generate shading effects on graphics elements using a texture samples. The graphics elements along with the shading effects are then rendered on a display device.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: Uzi Sarel, Piotr Rozenfeld
  • Patent number: 8253405
    Abstract: In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: August 28, 2012
    Inventors: Malay Trivedi, Jiang William, Brent D. Thomas, James T. Doyle, Rose Wang
  • Patent number: 8175203
    Abstract: A communication system comprises a receiver, which may generate broadcast coefficients that represent the characteristics of a channel using the channel information encoded in the segment synchronization units. The receiver may also use the channel information encoded in both the segment synchronization units and the field synchronization units to accurately determine the characteristics of a long channel.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: May 8, 2012
    Assignee: Intel Corporation
    Inventors: Jie Zhu, Ahmed Said, Roger Wu
  • Patent number: 8170631
    Abstract: In general, in one aspect, the disclosure describes an apparatus that includes two panels pivotally connected together. The panels can pivot from an open arrangement where the two panels lay side by side to a closed arrangement where the two panels lay one on top of another. The apparatus also includes a flexible display connected to the two panels and having a portion that is mechanically free from the two panels. The apparatus further includes a cavity to receive at least a portion of the free portion of the display when the panels are pivoted into the closed arrangement.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: May 1, 2012
    Assignee: Intel Corporation
    Inventors: Paul M. Aoki, Allison G. Woodruff
  • Patent number: 8145926
    Abstract: In general, in one aspect, the disclosure describes running a cooling fan within a computer at low speed while the computer is in low temperature operations (e.g., idle). The operation of the cooling fan may reduce processor (CPU) temperature enough to decrease processor leakage power, offsetting the power consumption of the fan, and possibly resulting in a net system power reduction. The benefit at the platform level increases further when considering the low efficiency of voltage regulation (VR) in this lower power regime, and potentially reductions in other components (e.g., graphics processor). The optimal fan speed is the speed at which the overall system power is reduced the most (e.g., processor power savings is greater than fan power utilized). The optimal temperature may be determined dynamically during operation or may be determined in manufacturing and applied statically during operation.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventors: Hee-jun Park, John Wallace
  • Patent number: 8143911
    Abstract: In general, in one aspect, the disclosure describes an apparatus having an averager to receive differential output voltages of a transmitter and generate an average transmitter output voltage. A comparator is to compare the average transmitter output voltage to a reference voltage and generate a difference therebetween. An integrator is to integrate the difference between the average transmitter output voltage and the reference voltage over time. The integrated difference is fed back to the transmitter to bias the transmitter.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventors: Zuoguo Wu, Feng Chen, Sanjay Dabral
  • Patent number: 8140474
    Abstract: In general, in one aspect, a method is disclosed that includes storing a superset of data available to a client having non volatile memory (NVM) on a distant hard drive. A subset of the data is maintained in the NVM on the client. The client controls the data stored on the distant hard drive and the data maintained in the NVM. A single merged directory/file tree image is generated for the content maintained in the NVM and the distant hard drive that is accessible to a user of the client and applications running thereon.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: March 20, 2012
    Assignee: Intel Corporation
    Inventors: Frank Hady, Brendan Traw, John W Carroll
  • Patent number: 8138635
    Abstract: In general, in one aspect, the disclosure describes an apparatus to enable direct injection of DC power from a renewable power source (e.g., solar) into an electronic device (e.g., computer). The DC power from the renewable source is injected into the electronic device on the DC side of a power supply used to provide power thereto. The DC power is injected into a tap that is installed between the power supply and a system board using the DC power. The apparatus may include a voltage regulator that converts the DC power to a DC voltage associated with the electronic device. The set point of the voltage regulator may be on the high side of the voltage range of the electronic device so that power is preferentially provided by the renewable source with additional power being provided by the power supply. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: March 20, 2012
    Inventor: Jason D. Campbell
  • Patent number: 8113348
    Abstract: A hybrid mounting card is disclosed that includes one or more receptacles form fit for respective portions of a medical device in order to receive and secure the respective portions of the medical device therein and a mounting card adapted to receive and secure the one or more receptacles. The one or more receptacles are configured on the mounting card to secure the medical device to the mounting card in a defined configuration. The use of the receptacles increases the types of medical devices that can be secured to mounting cards. The use of mounting cards enables medical devices to be stored in sterile barrier packaging systems that do not require custom thermoforming of an entire medical tray, such as medical pouches and standard blank medical trays.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: February 14, 2012
    Assignee: Mangar Industries, Inc.
    Inventor: Mark James Foster
  • Patent number: 8112265
    Abstract: In general, in one aspect, the disclosure describes creation of a randomization list that includes only a subset of the logic states of an integrated circuit (IC). The subset being selectable by signal so as to define logic states that can be randomized for specific events. The randomization list is during simulation to randomize the logic states defined therein to simulate a specific event occurring during operation of the IC. For example, the randomization list may include those signals that can be randomized upon exiting from a powered down state (e.g., deep power down, C6). The signals that can be randomized may be defined by excluding the signals that cannot be randomized (those still receiving power in the C6 mode). The contents of registers of the IC can be confirmed after the randomization and exit from the C6 mode.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: February 7, 2012
    Assignee: Intel Corporation
    Inventors: Maulik Joshi, Ivan Herrera Mejia, Joshua D. Louie
  • Patent number: 8110458
    Abstract: In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: February 7, 2012
    Assignee: Intel Corporation
    Inventors: Been-Yih Jin, Jack T. Kavalieros, Matthew V. Metz, Marko Radosavlievic, Robert S. Chau
  • Patent number: 8089788
    Abstract: In general, in one aspect, the disclosure describes a switched capacitor voltage regulator to generate a regulated output voltage based on varying input voltages. The regulator is capable of operating at one of a plurality of voltage conversion ratios and selection of the one of a plurality of voltage conversion ratios is based on an input voltage received. The switched capacitor voltage regulator provides a lossless (or substantially lossless) voltage conversion at the selected ratio. The ratio selected provides a down converted voltage closest to the regulated output voltage without going below the regulated output voltage. The down converted voltage is adjusted to the regulated output voltage using a resistive mechanism to dissipate excess power (lossy). Selection of an appropriate conversion ratio limits the resistive regulation and losses associated therewith and increases the efficiency of the switched capacitor voltage regulator.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: January 3, 2012
    Assignee: Intel Corporation
    Inventor: Rinkle Jain
  • Patent number: 8068566
    Abstract: In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple detection modes and multiple MIMO configurations.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: November 29, 2011
    Assignee: Intel Corporation
    Inventors: Raghavan Sudhakar, Veerendra Bhora, Kamal J. Koshy
  • Patent number: 8031764
    Abstract: In general, in one aspect, the disclosure describes a digital signal equalizer that includes a plurality of multiplexers. The number of multiplexers defines resolution of equalization. The plurality of multiplexers are configured in groups. The number of groups is based on number of taps, and the number of multiplexers associated with a particular group is based on equalization range for the group. The multiplexers in each group select a digital value associated with the cursor or a non-cursor tap associated with the group.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: October 4, 2011
    Assignee: Intel Corporation
    Inventors: Sitaraman V. Iyer, Henry Guo
  • Patent number: 8005026
    Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a first radio to communicate with a first wireless network and a second radio to communicate with a second wireless network. A controller is used to estimate signal to noise and interference ratio (SINR) for signal being received by the first radio when the second radio is transmitting. The controller is also to determine if the estimate meets a threshold. Transmissions are permitted from the second radio while the first radio is receiving if the threshold is met.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: August 23, 2011
    Assignee: Intel Corporation
    Inventors: Jing Zhu, Hsin-Yuo Liu, Leora Roth
  • Patent number: 7977248
    Abstract: In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickness to create a first plurality of fins in alignment with the first plurality of lines and the first resist layer is removed. A second resist layer is patterned on the hard mask as a second plurality of lines separated by a second defined pitch. The second plurality of lines is patterned between the first plurality of lines. The hard mask is etched to the portion of the formed thickness to create a second plurality of fins in alignment with the second plurality of lines. The first plurality of hard mask fins and the second plurality of hard mask fins are interwoven and have same thickness.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: July 12, 2011
    Assignee: Intel Corporation
    Inventors: Elliot Tan, Michael K. Harper, James Jeong
  • Patent number: 7973518
    Abstract: In general, in one aspect, the disclosure describes a voltage regulator (VR) that includes a first amplifier receiving a first reference voltage and a feedback voltage as inputs. A second amplifier receiving a second reference voltage and an output of the first amplifier as inputs. A drive component (e.g., transistor(s)) coupled to the second amplifier to drive current to an output based on an output of the second amplifier. A shunt component (e.g., transistor(s)) coupled to the first amplifier to shunt current from the output based on the output of the first amplifier. Current variations in the shunt component are controlled.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: July 5, 2011
    Assignee: Intel Corporation
    Inventors: Joseph Shor, Adam Zaidel, Noam Familia