Patents Represented by Attorney Ryder, Lu, Mazzeo and Konieczny, LLC
  • Patent number: 7971190
    Abstract: In general, in one aspect, the disclosure describes a method that includes interrupting a program running on a processor. The active instruction that was interrupted is identified. Event counts since a previous interrupt are harvested.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: June 28, 2011
    Assignee: Intel Corporation
    Inventors: Bob Davies, James Chapple, William K. Cheung, Guoping Wen, Carolyn Dase, Dan Nowlin
  • Patent number: 7885210
    Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a first radio to communicate with a first wireless network and a second radio to communicate with a second wireless network. The first wireless network transmits a map defining locations within an assigned spectrum data is to be communicated therebetween. An earliest possible location defined in map is such that the map can be parsed within the time it would take to get to the earliest possible location so that the radio can be turned off after receiving the map until the location defined in the map, and the second radio is active when the first radio is not.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventors: Xue Yang, Xiangying Yang, Xingang Guo
  • Patent number: 7872864
    Abstract: In general, in one aspect, the disclosure describes a laptop computer that can allow for enhanced cooling of a passively cooled notebook while maintaining the desired waterproof and dust resistance of the design. This is achieved by creating a separate cooling channel where air can flow through to provide cooling to an electronics enclosure connected thereto. The cooling channel may utilize membranes (e.g., hydrophobic membranes) to protect again water and dust penetration. In some cases, two fans are used in opposite directions in order to automatically clean the membranes from dust accumulation.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: January 18, 2011
    Assignee: Intel Corporation
    Inventors: Rajiv Mongia, James G. Hermerding
  • Patent number: 7825437
    Abstract: In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: November 2, 2010
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Suman Datta, Jack Kavalieros, Brian S. Doyle, Uday Shah
  • Patent number: 7826544
    Abstract: In general, in one aspect, the disclosure describes a method defining order and means in which physical parameters of a received OFDM signal may be detected. A fractional frequency offset is determined for the OFDM signal and is used to determine a coarse location for received signal preamble. A symbol boundary is determined based on the coarse location and the course location is used to determine preamble location. A preamble sequence and integer frequency offset is determined based on the preamble location.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: November 2, 2010
    Assignee: Intel Corporation
    Inventors: Eyal Bick, Uri Perlmutter
  • Patent number: 7820512
    Abstract: In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: October 26, 2010
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Suman Datta, Jack Kavalieros, Brian S. Doyle, Uday Shah
  • Patent number: 7814013
    Abstract: In general, in one aspect, parties associated with a merchant profile may be provided access to a system utilized to create merchant profiles. The system may accept data related to a merchant account from the parties and may validate the data. If any required information is missing or invalid the system may notify the parties. Once all the data is received and validated the system processes the data to create the merchant profile. The merchant profile may be stored in the system for the merchant. The merchant profile may be associated with a unique ID associated with a payment handler utilized by the merchant. The merchant or associated parties may utilize the unique ID to configure the payment handler including downloading processor software. The system may utilize the unique ID to manage and control use of the payment handlers and the processor applications.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: October 12, 2010
    Inventors: Leon N. Morsillo, Terry H. Zeigler
  • Patent number: 7808989
    Abstract: A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: October 5, 2010
    Inventors: Oleg Awsienko, Edward Butler, Gary L. McAlpine, David B. Minturn, Joseph Schaefer, Gary A. Solomon
  • Patent number: 7792960
    Abstract: In general, in one aspect, a method is described that includes monitoring data received from input devices. The received data from the input devices associated with an application is copied when the application is active. The data is converted to user commands. Commands used to update the application are received from the application. The converted user commands are compared to the commands from the application. Mismatching commands are reported to a remote server.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: September 7, 2010
    Assignee: Intel Corporation
    Inventors: Stephen D. Goglin, Travis T. Schluessler
  • Patent number: 7786769
    Abstract: In general, in one aspect, the disclosure describes an apparatus having on die circuitry coupled to at least one input port to receive a signal. A resistor is coupled to the on die circuitry and an off die power supply When a signal of sufficient amplitude is received by the on die circuitry the on die circuitry enables current to flow through the resister and reduces the voltage applied to the on die circuitry via the resister.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: August 31, 2010
    Assignee: Intel Corporation
    Inventors: Einat Surijan, Hemi Brann, Saba Rushdy
  • Patent number: 7787917
    Abstract: In general, in one aspect, the disclosure describes an apparatus that includes two panels pivotally connected together. The panels can pivot from an open arrangement where the two panels lay side by side to a closed arrangement where the two panels lay one on top of another. The apparatus also includes a flexible display connected to the two panels and having a portion that is mechanically free from the two panels. The apparatus further includes a cavity to receive at least a portion of the free portion of the display when the panels are pivoted into the closed arrangement.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: August 31, 2010
    Assignee: Intel Corporation
    Inventors: Paul M. Aoki, Allison G. Woodruff
  • Patent number: 7787398
    Abstract: In general, in one aspect, the disclosure describes a method that includes selecting an offset between start of communications of a first radio in a multi-radio platform (MRP) and start of communications of a second radio in the MRP. Synchronizing clocks of the first radio and the second radio to maintain the offset. Determining safe zones within the communications of the second radio based on configuration of the first radio and the second radio and the selected offset. The safe zones are locations that minimize conflicts between receiving operations of the first radio that are at fixed locations and transmitting operations of the second radio and transmitting operations of the first radio that are at fixed locations and receiving operations of the second radio.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: August 31, 2010
    Assignee: Intel Corporation
    Inventors: Changwen Liu, Xue Yang, Xingang Guo, Chul Kim
  • Patent number: 7767519
    Abstract: In general, in one aspect, a method includes forming a semiconductor fin. A first insulating layer is formed adjacent to the semiconductor fin. A second insulating layer is formed over the first insulating layer and the semiconductor fin. A first trench is formed in the second insulating layer and the first insulating layer therebelow. The first trench is filed with a polymer. A third insulating layer is formed over the polymer. A second trench is formed in the third insulating layer, wherein the second trench is above the first trench and extends laterally therefrom. The polymer is removed from the first trench. A capacitor is formed within the first and the second trenches.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: August 3, 2010
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Dinesh Somasekhar, Robert S. Chau
  • Patent number: 7765323
    Abstract: In general, in one aspect, the disclosure describes a method to assign unique addresses to each sink device in a content network based on port numbers of a source and branch devices in the network. Sink devices connected to a port on the source or the branch devices are assigned a corresponding port number as a sink address. Branch devices connected to a port on the source or higher level branch devices have a corresponding port number prepended to the previously assigned sink addresses.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: July 27, 2010
    Assignee: Intel Corporation
    Inventor: Srikanth Kambhatla
  • Patent number: 7745270
    Abstract: In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A polysilicon layer is formed over the silicon germanium layer and is polished. The polysilicon layer over the first work function metal layer is thicker than the polysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the polysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: June 29, 2010
    Assignee: Intel Corporation
    Inventors: Uday Shah, Brian S. Doyle, Jack T. Kavalieros, Been-Yih Jin
  • Patent number: 7727830
    Abstract: In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: June 1, 2010
    Assignee: Intel Corporation
    Inventors: Been-Yih Jin, Jack T. Kavalieros, Matthew V. Metz, Marko Radosavlievic, Robert S. Chau
  • Patent number: 7719982
    Abstract: In some embodiments a switching device is disclosed that includes one or more ingress queues to queue data received from external sources while waiting to forward the data to one or more egress queues. The egress queues queue the data while waiting to transmit the data to external sources. The switching device also includes a switch fabric to provide connectivity between the one or more ingress queues and the one or more egress queues. The switching device further includes an ingress flow-control manager to monitor flow-control state of the one or more ingress queues, and to detect and recover from loss of ON flow-control messages. Other embodiments are otherwise disclosed herein.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventor: Anujan Varma
  • Patent number: 7698498
    Abstract: In some embodiments a memory controller is disclosed that includes at least one command/address input buffer to receive commands and addresses. The addresses specify a memory bank and a location within the memory bank. An arbiter, coupled to the at least one command/address input buffer, merges commands and addresses from the at least one command/address input buffer and sorts the commands and addresses based on the addresses specified. A plurality of bank buffers, coupled to the arbiter and associated with memory banks, receive commands and addresses for their associated memory banks. A scheduler, coupled to the plurality of bank buffers, groups commands and addresses based on an examination of at least one command and address from the bank buffers. Other embodiments are otherwise disclosed herein.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Dharmin Y. Parikh, Karthik Vaithianathan, Gary Lavelle, Atul Kwatra
  • Patent number: 7691718
    Abstract: In general, in one aspect, a method includes forming a semiconductor substrate having an N+ diffusion region, a shallow trench isolation (STI) region adjacent to the N+ diffusion region, and a blocked salicide poly resistor (BSR) region over the STI region. An oxide layer is over the substrate. A nitride layer is formed over the oxide layer and is annealed. A resist layer is patterned on the annealed nitride layer, wherein the resist layer covers a portion of the BSR region. The annealed nitride layer is etched using the resist layer as a pattern. The resist layer is removed and the oxide layer is etched using the annealed nitride layer as a pattern. Germanium pre-amorphization is implanted into the substrate, wherein the oxide and the annealed nitride layers protect a portion of the BSR region from the implanting.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: April 6, 2010
    Assignee: Intel Corporation
    Inventors: Joodong Park, Chia-Hong Jan, Paul Reese
  • Patent number: 7683844
    Abstract: In general, in one aspect, the disclosure describes a semiconductor antenna having a plurality of antenna elements and a switching network formed in the same semiconductor die. The switching network is to control activation of the antenna elements.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: March 23, 2010
    Assignee: Intel Corporation
    Inventors: Siavash Alamouti, Alexander A. Maltsev, Nikolav Chistyakov, Alexey Artemenko