Abstract: Method and semiconductor structure to avoid latch-up. Method includes identifying at least one high voltage device on a semiconductor chip, identifying a circuit on the semiconductor chip separated from the identified at least one high voltage device by a guard ring, evaluating the circuit for a latch-up condition, and when the latch-up condition occurs, adjusting the contact-circuit spacing in the circuit.
Type:
Grant
Filed:
February 14, 2008
Date of Patent:
January 31, 2012
Assignee:
International Business Machines Corporation
Abstract: Method of generating cyclic redundancy checks (CRCs) for a message with N data blocks. The method includes calculating a partial CRC for an out of order data block and storing the result, generating, using a division operation, a CRC remainder multiplier associated with the out of order data block and storing the result, repeating the calculating and generating steps until all N data blocks for the message are received, and combining the results of the calculating step and the generating step.
Type:
Grant
Filed:
March 3, 2008
Date of Patent:
January 31, 2012
Assignee:
International Business Machines Corporation
Inventors:
Richard E. Anderson, Christos John Georgiou, Peter A. Sandon
Abstract: A method for operating a resonance-measuring system, in particular, a Coriolis mass flowmeter, having at least one oscillation element, at least one oscillation driver and at least one oscillation sensor, the oscillation element being excited to oscillation in at least one control using at least one control loop by at least one oscillation driver being excited by at least one excitation signal and the excited oscillations of the oscillation element being detected by the oscillation sensors as at least one response signal. At least one set variable of the closed loop is varied in a pre-determined manner and by evaluating at least one resulting excitation signal and/or at least one resulting response signal with the help of a mathematical model of the resonance-measuring system, at least one parameter of the excited eigenform is selectively identified.
Abstract: The invention generally relates to design verification, and more particularly to verification of non-deterministic behavior of a design under test. A method includes predicting a plurality of behaviors of a design under test (DUT), and forking respective verification tasks for each one of the plurality of behaviors. The method further includes verifying an actual behavior of the DUT with each of the verification tasks, and terminating a respective one of the verification tasks when the actual behavior of the DUT does not conform to the respective one of the verification tasks.
Type:
Grant
Filed:
February 20, 2008
Date of Patent:
January 24, 2012
Assignee:
International Business Machines Corporation
Inventors:
Jesse E. Craig, Suzanne Granato, Francis A. Kampf, Barbara L. Powers
Abstract: A panel, in particular a floor panel, includes a core of a wood material or wood material/plastic mixture. The panel includes a top side and an underside. The panel has a profile corresponding to one another on at least two side edges (I, II) lying opposite one another, such that two identically embodied panels can be joined and locked to one another through an essentially vertical joining movement in the horizontal and vertical direction. The locking in the horizontal direction can be effected by a hook connection with an upper locking section having a hook element and a lower locking section having a hook element. The locking in the vertical direction can be effected by at least one spring element that can be moved in the horizontal direction. During the joining movement the at least one spring element snaps in behind a locking edge extending essentially in the horizontal direction.
Abstract: A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.
Type:
Grant
Filed:
August 14, 2008
Date of Patent:
January 24, 2012
Assignee:
International Business Machines Corporation
Inventors:
David S. Collins, Kai D. Feng, Zhong-Xiang He, Peter J. Lindgren, Robert M. Rassel
Abstract: A profiled strip system, in particular for closing off edges and/or for concealing joints, for a surface covering, having a lower base profile and an upper cover profile, wherein a latching connection is provided between the base profile and the cover profile to connect them, wherein the latching connection has a latching receptacle, which has two leg profiles with mutually opposite latching regions, and a latching profile which can be latched into the latching receptacle and which is provided with multiple latching points, and wherein each latching region has at least two latching points. The latching regions are provided only in certain regions on the leg profiles and portions of the leg profiles that are free of latching regions are situated at far from one another such that the latching region-free sections of the leg profiles further from one another than the latching regions.
Abstract: A vehicle roof for a passenger car, the vehicle roof having a modular, multishell structure, the vehicle roof including a variably configurable functional shell for providing stiffness to the vehicle roof and configured to be directly attached to a body shell of the vehicle and for variable accommodation of functional elements; an outside roof skin configured to be fixed to an outside surface of the functional shell with a fixing means; and at least one inside lining element configured to be fixed to an inside surface of the functional shell.
Abstract: A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from tools processing the wafers or wafer lots. A system for increasing overall yield in semiconductor manufacturing includes a module for routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from the tools processing the wafers or wafer lots.
Type:
Grant
Filed:
June 24, 2008
Date of Patent:
January 10, 2012
Assignee:
International Business Machines Corporation
Inventors:
Xu Ouyang, Oleg Gluschenkov, Yunsheng Song, Keith Kwong Hon Wong
Abstract: A method of laying out features for alternating aperture phase shift masks. The method includes defining features on a grid of a uniform basic pitch, orienting the features such that those of the features defined, at least in part, by phase shifting shapes are oriented along a primary direction, and spacing two features terminating adjacent one another such that the two features have space between them sufficient to prevent phase conflicts if both of the two features are defined, at least in part, by phase shifting shapes.
Type:
Grant
Filed:
October 22, 2008
Date of Patent:
January 10, 2012
Assignee:
International Business Machines Corporation
Abstract: A process for producing an alkylbenzene hydroperoxide from an alkylbenzene solution containing 0.01 to 10 mmol/kg of phenols by subjecting the solution to oxidation with an oxygen-containing gas, including allowing a compound represented by formula (I) to be present in the alkylbenzene solution: wherein R1, R2, R3, R4 and R5 independently represent a hydrogen atom, an alkyl group or an aryl group and may combine with each other to form a non-aromatic ring, the molar ratio of the compound represented by formula (I) to the phenols in the alkylbenzene solution being 0.4 mol/mol or higher; is advantageous in providing economical and high-yield production of an alkylbenzene hydroperoxide.
Abstract: A method for producing a building board. The method includes applying synthetic-resin layers to the top side and/or the bottom side of a support board made of a wood material or a mixture of wood material and plastic. The layered structure is compressed under the impact of pressure and temperature. At least one of the synthetic-resin layers expands during compressing.
Abstract: A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.
Type:
Grant
Filed:
October 19, 2007
Date of Patent:
January 10, 2012
Assignee:
International Business Machines Corporation
Inventors:
Jeanne P. Bickford, John R. Goss, Nazmul Habib, Robert McMahon
Abstract: A computerized tomography apparatus and program for obtaining a cross-sectional image corresponding to projections are provided in which, for a temporary cross-sectional image f(x, y) obtained in some manner, an evaluation function E is defined which includes differences between projections calculated from f(x, y) and measured projections, and f(x, y) is changed in a manner which substantially decreases E. The computerized tomography apparatus and program are characterized in which a back projection operation, which is required by conventional computerized tomography, is not essentially required. The computerized tomography apparatus and program are particularly effective in removal or reduction of metal artifacts, aliasing artifacts and the like.
Type:
Grant
Filed:
November 13, 2007
Date of Patent:
January 3, 2012
Assignee:
National University Corporation Kyoto Institute of Technology
Abstract: An apparatus for sensing at least one analyte in a gas. The apparatus includes a thermoelectric sensor having a layer of at least one analyte interactant that increases or decreases in temperature and at least one thermopile having a first contact pad and a second contact pad, wherein the analyte contacts the interactant and produces or consumes heat, which is transmitted to the thermopile, produces a voltage difference and measures the analyte.
Abstract: A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, fanning an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.
Type:
Grant
Filed:
November 4, 2010
Date of Patent:
January 3, 2012
Assignee:
International Business Machines Corporation
Inventors:
Karl W. Barth, Jeffrey P. Gambino, Tom C. Lee, Kevin S. Petrarca
Abstract: An overvoltage protection element (1) includes a housing (2), two terminals (3, 4) for electrical connection of the overvoltage protection element (1) to current or signal paths to be protected, and an arrester (5, 6), including a varistor, located within the housing (2). In addition to providing a simple structure and installation, the overvoltage protection element (1) is especially well adapted to thermal and dynamic loads, so that no damage to the overvoltage protection element (1) occurs to the outside, wherein the housing (2) includes two metal shells (7, 8) electrically connected to a terminal region (9, 10) of the arrester (5, 6).
Abstract: A method implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable medium being operable to determine at least one data center condition and determine or estimate a current energy cost. Additionally, the method includes dynamically control a heating, ventilation and air conditioning (HVAC) system of the data center based on the determined at least one data center condition and the determined or estimated current energy cost.
Type:
Grant
Filed:
July 11, 2008
Date of Patent:
January 3, 2012
Assignee:
International Business Machines Corporation
Inventors:
Christopher J. Dawson, Vincenzo V. Diluoffo, Rick A. Hamilton, II, Michael D. Kendzierski
Abstract: The present disclosure enables phenol recovery, purification and recycle in a simple, economic manner from waste streams from, for example, a phenol/acetone production process, e.g., a phenol/acetone plant or an upstream cumene hydroperoxide cleavage process step, and BPA production step, for use in the reaction with acetone to produce BPA. The disclosure therefore reduces the overall consumption of phenol in the production of BPA.
Abstract: A bowling bumper system is provided. The bowling bumper system and more particularly an actuator or actuator assembly is decoupled from the bumpers, themselves, and configured to move the bumpers into an extended or retracted position.
Type:
Grant
Filed:
November 3, 2008
Date of Patent:
December 27, 2011
Assignee:
QUBICAAMF Worldwide LLC
Inventors:
Samuel R. Namala, David A. McCall, Charles Anton Lee, Patrick J. Reitelbach