Abstract: A method and system for reducing the inductance on an integrated circuit. The method and system comprises providing a first differential line, including a first input and a first output, the first differential line including at least two bondwire traces which are coupled in parallel. The method and system also comprises providing a second differential line including a second input and a second output, the second differential line including at least two bondwire traces which are coupled in parallel, the first differential line being of opposite polarity to the second differential line. The method and system further comprises cross-coupling of the first input with the second input and the first output with the second output to reduce the inductance caused by bondwire traces. A technique in accordance with the invention uses the coupling factor K to help to further reduce the inductance.
Abstract: An angular rate sensor is disclosed. The angular rate sensor comprises a substrate and a drive subsystem partially supported by a substrate. The drive subsystem includes at least one spring, at least one anchor, and at least one mass; the at least one mass of the drive subsystem is oscillated by at least one actuator along a first axis. Coriolis force acts on moving the drive subsystem along or around a second axis in response to angular velocity of the substrate around the third axis. The angular rate sensor also includes a sense subsystem partially supported by a substrate. The sense subsystem includes at least one spring, at least one anchor, and at least one mass.
Abstract: Phase-locked loop charge pump driven by low voltage input. In one aspect, a phase-locked loop circuit includes a phase frequency detector operating at a low voltage and providing low-voltage sourcing control signals and low-voltage sinking control signals at the low voltage. A charge pump operates at a high voltage and includes a sourcing control circuit coupled to the low-voltage sourcing control signals and selectively causing the charge pump to source the sourcing current to an output of the charge pump based on the low-voltage sourcing control signals. The charge pump also includes a sinking control circuit that receives the low-voltage sinking control signals and selectively causes the charge pump to sink the sinking current from the output of the charge pump based on the low-voltage sinking control signals.
Type:
Grant
Filed:
March 5, 2010
Date of Patent:
September 20, 2011
Assignee:
Ralink Technology Corporation
Inventors:
I-chang Wu, Chungwen Lo, Keng Leong Fong
Abstract: A thermal field emission cathode which is employed in an electron microscope, a critical dimension examine tool, an electron beam lithograph machine, an electron beam tester and other electron beam related systems as an electron source is disclosed. Embodiments disclose changing coating shape, coating position and shorten emitter length to extend the lifetime of the field emission cathode.
Abstract: A supercomputer processing system is provided that is configured to execute a plurality of simulations through transaction processing. The supercomputer processing system includes a supercomputer configured to execute a first simulation of the plurality of simulations and generate an output based upon execution of the first simulation, and a transaction hub. The transaction hub includes a relational database configured to store the output of the first simulation, and an application server having a service-oriented architecture (SOA) that supports an event triggering service. The event triggering service is configured to detect the output of the first simulation and automatically trigger the supercomputer to execute a second simulation of the plurality of simulations using the output of the first simulation stored in the relational database.
Type:
Grant
Filed:
July 23, 2007
Date of Patent:
September 20, 2011
Assignee:
International Business Machines Corporation
Inventors:
Frederick D. Busche, Kirk A. Boothe, Shahinaz Nabih Carson, Alexander Darius Zekulin
Abstract: An activity log is displayed in a dedicated area in a business to consumer e-commerce web site that tracks activities that occur during a current e-commerce account session. The activity log is updated automatically, without requiring user intervention. The activity log displays information such as the activity type, the activity name, and the time the activity was performed. The activity log may also provide an option for the user to view details about or to undo an individual activity. The activity log tracks activities that would conventionally be lost from view, such as the removal of items from a list and the changing of the password. In addition, the activity log automatically displays updates that are not conventionally available, such as greater granularity in the status of an asynchronous transaction.
Type:
Grant
Filed:
June 30, 2008
Date of Patent:
September 6, 2011
Assignee:
International Business Machines Corporation
Abstract: The present invention relates generally to data retrieval, and more particularly but not exclusively to obtaining referentially converted user data having user-defined data types. In one implementation, the present invention is a method for retrieving user data in a data system using one or more application programs for defining a layout for each user data type, defining one or more conversion routines for non-standard data types, calling a coordination call to map standard and non-standard data types, and retrieve the user data from the data storage device.
Type:
Grant
Filed:
January 2, 2008
Date of Patent:
September 6, 2011
Assignee:
International Business Machines Corporation
Inventors:
Kiran Challapalli, Kyle Jeffrey Charlet, Christopher M. Holtz, William W. Li
Abstract: Embodiments of the invention generally relate to a method for forming a multi-layered material during a continuous chemical vapor deposition (CVD) process. In one embodiment, a method for forming a multi-layered material during a continuous CVD process is provided which includes continuously advancing a plurality of wafers through a deposition system having at least four deposition zones. Multiple layers of materials are deposited on each wafer, such that one layer is deposited at each deposition zone. The methods provide advancing each wafer through each deposition zone while depositing a first layer from the first deposition zone, a second layer from the second deposition zone, a third layer from the third deposition zone, and a fourth layer from the fourth deposition zone. Embodiments described herein may be utilized to form an assortment of materials on wafers or substrates, especially for forming Group III/V materials on GaAs wafers.
Abstract: A method and system for controlling an overlay shift on an integrated circuit is disclosed. The method and system comprises utilizing a scanning electron microscope (SEM) to measure the overlay shift between a first mask and a second mask of the circuit after a second mask and comparing the overlay shift to information about the integrated circuit in a database. The method and system includes providing a control mechanism to analyze the overlay shift and feed forward to the fabrication process before a third mask for error correction. A system and method in accordance with the present invention advantageously utilizes a scanning electron microscope (SEM) image overlay measurement after the fabrication process such as etching and chemical mechanical polishing (CMP).
Abstract: A solid state disk system is disclosed. The system comprises a user token and at least one level secure virtual storage controller, coupled to the host system. The system includes a plurality of virtual storage devices coupled to at least one secure virtual storage controller. A system and method in accordance with the present invention could be utilized in flash based storage, disk storage systems, portable storage devices, corporate storage systems, PCs, servers, wireless storage, and multimedia storage systems.
Type:
Grant
Filed:
May 9, 2007
Date of Patent:
August 30, 2011
Assignee:
Kingston Technology Corporation
Inventors:
Ben Wei Chen, Yungteh Chien, Choon Tak Tang
Abstract: A power switch circuit and method is provided for having the capability of (1) a power switch circuit having a POR in which the switch is enabled at a predetermined voltage such that the switch is unable to be activated when a minimum lower input voltage is not achieved, to avoid potential conflicts in synchronization and resets with other integrated circuits or chips of an affected system; (2) a POR designed with a delay circuit providing for coordinated stabilization of the power switch before each ON-OFF transition period; (3) using a controlled peaking current in the POR circuit to provide precise RC delay to avoid instability during transition; and (4) a POR providing an externally controlled voltage to power-up other components in the system when energizing of the first component occurs satisfactorily.
Abstract: The present invention provides a computer-readable medium and system for selecting a set of n-grams for indexing string data in a DBMS system. Aspects of the invention include providing a set of candidate n-grams, each n-gram comprising a sequence of characters; identifying sample queries having character strings containing the candidate n-grams; and based on the set of candidate n-grams, the sample queries, database records, and an n-gram space constraint, automatically selecting, given the space constraint, a minimal set of an n-grams from the set of candidate n-grams that minimizes the number of false hits for the set of sample queries had the sample queries been executed against the database records.
Type:
Grant
Filed:
November 4, 2008
Date of Patent:
August 16, 2011
Assignee:
International Business Machines Corporation
Abstract: An embodiment of the present invention includes a transceiver for use in a multi-input-multi-output (MIMO) Orthogonal Frequency Domain Multiplexing (OFDM) wireless communication system. The transceiver decodes and remodulates certain signal fields and uses the same to update the coefficients of a frequency equalizer thereby improving channel estimation and extending training.
Abstract: A system and method for interfacing a portable electronic device, having a plurality of commands including a plurality of resource commands and a plurality of local commands, with a remote resource over a costed communications channel includes processing the plurality of commands on the device without communicating any of the resource commands over the channel to the remote resource while aggregating the resource commands to produce a set of resource commands; communicating the set of resource commands to the remote resource over the channel to produce a resource output responsive to the set of resource commands; communicating the resource output to the device from the remote resource; and processing the resource output on the device using the set of local commands.
Type:
Grant
Filed:
September 27, 2002
Date of Patent:
August 2, 2011
Assignee:
International Business Machines Corporation
Inventors:
Josephine Miu Cheng, Chi-Pei Michael Hsing, Frank Meng
Abstract: A shape-molding structure of a memory card comprises a circuit substrate, at least one chip, and an encapsulant covering. The upper and lower surfaces of the circuit substrate have a circuit layer and a plurality of electric contacts, respectively. The chip is located on the upper surface of the circuit substrate and electrically connected with the circuit layer. The encapsulant covering is formed by using a mold to press encapsulant entering at least one encapsulant inlet provided on at least one side surface of the circuit substrate. The encapsulant covering encapsulates all the above components with only the electric contacts exposed. A trace mark of the encapsulant inlet remaining on the encapsulant covering is then cut to obtain a shape-molding structure of memory card with an smooth and intact outer appearance.
Type:
Grant
Filed:
July 22, 2009
Date of Patent:
August 2, 2011
Assignee:
Kingston Technology Corporation
Inventors:
Ben Wei Chen, Jin S. Wang, David Hong-Dien Chen
Abstract: A method for connecting a programmable device (PD) and an electronic component (EC) based on a protocol, including: obtaining a signal group of the protocol having a group constraint, a first pin definition including an electrical constraint and a logical constraint, and a second pin definition; mapping the first pin definition to a first pin of the PD based on the electrical constraint, the logical constraint, and the group constraint; identifying a first pin of the EC to connect with the first pin of the PD based on the electrical constraint, the logical constraint, the group constraint, and a connection preference; generating a first connection between the first pin of the EC and a second pin of the PD based on the electrical constraint, the logical constraint, the group constraint, and the connection preference; and storing the first connection in an edge list.
Type:
Grant
Filed:
January 9, 2009
Date of Patent:
August 2, 2011
Assignee:
Cadence Design Systems, Inc.
Inventors:
Nagesh Chandrasekaran Gupta, Ravi Srinivasa Vedula
Abstract: The present invention discloses a memory system comprising a plurality of crystals, and at least two conductors. The at least two conductors being orthogonal to each other. Wherein at least one of the plurality of crystals are bounded by the orthogonal intersection of the at least two conductors.
Abstract: The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to predictive, pre-fabrication methodologies for determining inefficiencies in an integrated circuit (IC) design. The present invention, in one or more implementations, provides an effective pre-production methodology for predicting the efficiency and behavior of a designed ESD protective circuit and testing the ESD protective circuit with a simulated IC. The method of the present invention yields predictive results that have been comparatively tested.
Abstract: The present invention is one or more implementations is a method of fabricating a semiconductor for improved oxide thickness control, defining a process tool, determining and evaluating performance variables, determining a performance impact factor and thereafter modifying control of the process tool in the fabrication process to operate in direct relation to the determined results of the present invention. The present invention sets forth definitive advantages in reducing engineering time, improving process controls and improving cycle-times.
Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.
Type:
Grant
Filed:
October 31, 2008
Date of Patent:
July 19, 2011
Assignee:
Cadence Design Systems, Inc.
Inventors:
Amir Lehavot, Vinaya Kumar Singh, Joezac John Zachariah, Jose Barandiaran, Axel Siegfried Scherer