Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium.

Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.

Abstract: A pixel sensor cell of improved dynamic range and a design structure including the pixel sensor cell embodied in a machine readable medium are provided. The pixel cell comprises a coupling transistor that couples a capacitor device to a photosensing region (e.g., photodiode) of the pixel cell, the photodiode being coupled to a transfer gate and one terminal of the coupling transistor. In operation, the additional capacitance is coupled to the pixel cell photodiode when the voltage on the photodiode is drawn down to the substrate potential. Thus, the added capacitance is only connected to the imager cell when the cell is nearing its charge capacity. Otherwise, the cell has a low capacitance and low leakage. In an additional embodiment, a terminal of the capacitor is coupled to a “pulsed” supply voltage signal that enables substantially full depletion of stored charge from the capacitor to the photosensing region during a read out operation of the pixel sensor cell.

Abstract: A network terminal device is configured to include a plurality of network applications that generate process instructions to cause devices on a network to execute processes, a storage unit that stores common network configuration information of the plurality of network applications, and a network terminal device where each of the plurality of network applications is capable of reading out the common network configuration information from the storage unit and reflecting the same in its own network configuration. Each application may transmit the process instructions to the device on the network based on the network configuration.

Abstract: A position estimating device (4) which estimates the position of an object by comparing a receiving pattern obtained from ID transmitters (2a, 2b, . . . ) and ID receivers (3a, 3b, . . . ) installed in an environment with a prestored receiving pattern. Position of an object equipped with no extra device can be estimated only with the ID transmitters and ID receivers installed in an environment even in an indoor multipath environment by utilizing a fact that a receiving pattern obtained from ID transmitters (2a, 2b, . . . ) and ID receivers (3a, 3b, . . . ) installed in an environment changes depending on the position of the object.

Abstract: A management device is connected to image formation devices, each having at least one network interface, via a network.

Abstract: This endoscope treatment tool insertion-extraction system is provided with: a first treatment tool and a second treatment tool which are insertable into and retractable from a forceps channel of an endoscope; a first insertion-extraction mechanism which feeds the first treatment tool into the forceps channel or removes the first treatment tool from the forceps channel; a second insertion-extraction mechanism which feeds the second treatment tool into the forceps channel or removes the second treatment tool from the forceps channel; one driving section which drives the first insertion-extraction mechanism and the second insertion-extraction; and a selection section which selectively engage the driving section with one of the first insertion-extraction mechanism and the second insertion-extraction mechanism.

Abstract: The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

Abstract: The present invention relates to a process for the production of a fat composition for confectionery or baking applications. According to this process, a starting fat composition containing palm oil or a palm oil fraction and having the following composition: (1) a glyceride composition with—a S2U content between 47 and 75 wt. %, —a SU2+U3 content <40 wt. %, —a S3 content between 1 and 15 wt. %, —a diglyceride content of 3 to 12 wt. %, the glyceride contents being expressed as wt. % with respect to the total amount of di- and triglycerides in which S means a saturated fatty acid with A hydrocarbon chain length of 14-24 carbon atoms and U means unsaturated fatty acid with a hydrocarbon chain length of 14-24 carbon atoms and (2) a total content of unsaturated fatty acids of less than 55 wt. %, preferably less than 50 wt. %, more preferably less than 48 wt. %, is subjected to a catalytic hydrogenation so as to obtain a first fat with a trans fatty acid content <wt. %, preferably <10 wt.

Abstract: The invention includes a design structure embodied in a computer readable medium for performing a method for inserting a scan chain into a VLSI circuit design. The scan chain structure, or structures, are included in the design structure for the VLSI circuit design. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain. Buffer circuit control elements control the first flip-flop (L1) to switch between scan mode or low power leakage mode. The switching occurs in only one clock cycle.

Abstract: A method of and system for rateless source coding are disclosed. The method comprises the steps of providing a set of low-density parity check (LDPC) codes, each of which accepts a range of data input lengths and a range of target compression rates; identifying a data input having a data input length; and identifying a desired compression rate. The method comprises the further steps of selecting one of said LDPC codes based on said data input length and desired compression rate; encoding the data input, using the selected LDPC code, to generate a sequence of data values; and puncturing some of said encoded data values to achieve the desired compression rate. Preferably, the encoding step includes the steps of generating a syndrome and a parity sequence from the data input, puncturing the generated parity sequence, and mixing a remaining portion of the data input with the punctuated parity sequence.

Abstract: A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.

Abstract: A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.

Abstract: The present invention provides a method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating. In general terms, a method is provided that includes providing at least one patternable low-k material on a surface of an inorganic antireflective coating that is located atop a substrate. The inorganic ARC is liquid deposited and comprises a polymer that has at least one monomer unit comprising the formula M-R1 wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La and R1 is a chromophore. At least one interconnect pattern is formed within the at least one patternable low-k material and thereafter the at least one patternable low-k material is cured.

Abstract: A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

Abstract: A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.

Abstract: The invention relates to a fluorinated derivate of quinolin-2(1H)-one (I), to a method for preparing the same, and to the use thereof as an intermediate in the synthesis of 7-fluoro-2-oxo-4-[2-[4-[thieno[3,2-c]pyridine-4-yl)piperazin-1-yl]ethyl]-1,2-dihydro-quinolin-1-acetamide. The invention also relates to the pharmaceutically acceptable salts thereof.

Abstract: The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.

Abstract: An endoscope of the present invention includes an insert section inserted in a subject body, an operation section provided at a base end of the insert section, a control process section provided in the operation section, for controlling an image pickup section for capturing a subject body image and a predetermined function in the operation section, a signal circuit extending from the control process section, and a connection section provided to the operation section, for allowing detachable connection of a tube unit through which at least one duct line is inserted.

Abstract: The present invention provides a node capable of preventing the problems caused by switching between traffic communication paths when a link failure occurs. According to an embodiment of the invention, among ports of a node 10, ports P1 and P2 connected to a link between the node 10 and a node 20 are registered in a virtual port VP1, and ports P3 and P4 connected to a link between the node 10 and the node 30 are registered in a virtual port VP2. The virtual ports VP1 and VP2 are registered in a virtual port VP3 allocated to a virtual LAG group. When one link between the node 10 and the node 20 is disconnected, the node 10 transmits frames, which have been transmitted from a physical port connected to the link, from the virtual port including the physical port, among the virtual ports belonging to the virtual port VP3 allocated to the virtual LAG group.