Patents Represented by Law Firm Seed and Berry
  • Patent number: 5961591
    Abstract: A downloading facility for downloading data while rejection of its use may be overridden is provided. In a preferred embodiment, the downloading facility receives a request to retrieve and use an identified body of data. In response, the facility initiates the retrieval of the identified body of data. At a time during its retrieval, use of the identified body of data is automatically rejected. In response to this rejection, the facility provides a user interface for authorizing the use of the identified body of data. During the provision of this user interface, retrieval of the identified body of data proceeds. When the provided user interface is used to authorize the use of the identified body of data, the facility uses the retrieved identified body of data in accordance with the request.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: October 5, 1999
    Assignee: Microsoft Corporation
    Inventors: Gregory Alan Jones, Satoshi Nakajima, Scott E. Berkun, Christopher M. Franklin
  • Patent number: 5958720
    Abstract: A substantially pure protein that is a member of the apoptotic Ced-3/Ice cysteine protease gene family, Mch2.alpha., and an inactive isoform of it, Mch2.beta., are disclosed. Isolated nucleic acid molecules that encode Mch2.alpha. and Mch2.beta., respectively, are disclosed. Pharmaceutical compositions comprising a pharmaceutically acceptable carrier in combination with the protein or the nucleic acid molecules are disclosed. Fragments of nucleic acid molecules that encode Mch2.alpha. and Mch2.beta. having at least 10 nucleotides and oligonucleotide molecule comprising a nucleotide sequence complimentary to a nucleotide sequence of at least 10 nucleotides are disclosed. Recombinant expression vectors that comprise the nucleic acid molecule that encode Mch2.alpha. or Mch2.beta., and host cells that comprise such recombinant vectors are disclosed. Antibodies that bind to an epitope on Mch2.alpha. and/or Mch2.beta. are disclosed. Methods of identifying inhibitors, activators and substrates of Mch2.alpha.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: September 28, 1999
    Assignee: Thomas Jefferson University
    Inventors: Gerald Litwack, Emad S. Alnemri, Teresa Fernandez-Alnemri
  • Patent number: 5957318
    Abstract: The present invention relates to a brewing vessel comprising a manhole opening which is closable by a lockable lid. To obtain a simple locking mechanism which, in particular, does not create any unaccessible space, the locking ring is supported on the outside of the frame and comprises at least one locking bolt which cooperates with a recess formed in a collar of the lid.
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: September 28, 1999
    Assignee: Anton Steinecker Maschinenfabrik GmbH
    Inventors: Friedrich Banke, Harald Gratzer, Rudolf Flossmann
  • Patent number: 5957980
    Abstract: A reinforcement assembly to reinforce a selected site on a body, and methods of making and using such a universal reinforcement assembly. Several embodiments of reinforcement assemblies in accordance with the principles of the invention are well suited to support or reinforce laminated structures. In one embodiment, the reinforcement assembly has a reinforcement member configured to be attached to the selected site on the body and a universal attachment medium separately bonded to the reinforcement member. The reinforcement member may be a plate composed of a molding compound, a high density polymer, or another suitable high-strength material. The universal attachment medium, more specifically, may have a first section bonded to the reinforcement member and a second section extending from the reinforcement member to cover an area of the body substantially surrounding the selected site.
    Type: Grant
    Filed: September 9, 1997
    Date of Patent: September 28, 1999
    Assignee: Model & Instrument Development Corporation
    Inventors: Guy Houser, Stewart L. Atkinson
  • Patent number: 5957750
    Abstract: A method and apparatus for controlling a polishing characteristic of a polishing pad used in planarization of a substrate. The method preferably includes controlling the temperature of a planarizing surface of the polishing pad so that waste matter accumulations on the planarizing surface soften and/or become more soluble, and/or material comprising the planarizing surface attains approximately its glass transition temperature. The waste matter accumulations and/or a portion of the planarizing surface are in this way softened and more easily removed. The planarizing surface is either heated directly by directing a flow of heated planarizing liquid or heated air to the planarizing surface or indirectly by heating a support surface beneath the polishing pad or by heating the air proximate to the polishing pad.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: September 28, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Thad Lee Brunelli
  • Patent number: 5959935
    Abstract: The invention refers to a generating circuit for synchronization signals to regulate the read phase of memory cells in electronic devices with an integrated memory on a semiconductor, of the type controlled by a switching of logical states on a left ATD bus and a right ATD bus and comprising a left and a right section inserted between a first and a second voltage reference and connected respectively to the left and the right ATD bus, the sections being connected at the input to a reference-voltage generated and at the output to an ATD generator.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: September 28, 1999
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Luigi Pascucci
  • Patent number: 5960168
    Abstract: Facilities are provided within an operating system for supporting deferred printing of print jobs. The process of spooling a print job and the process of despooling the print job are decoupled, such that a printer need not be available at the time of spooling. Print jobs are spooled in a device-independent format, such as the enhanced metafile format. The print jobs may be spooled without a printer driver being installed for a target printer or without the target printer being connected to the system. Later, when the target printer becomes available, the print job is despooled and printed. A configuration database holds different printer configurations that list available printers in different environments. For example, a user may have a different configuration for printers available when he uses his computer at home, at work and on the road, respectively. The configurations help the user to identify the printers that are currently available and those that are available in other settings.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: September 28, 1999
    Assignee: Microsoft Corporation
    Inventors: Lin F. Shaw, Chia-Chi Teng, Kenneth W. Sykes, Raymond E. Endres
  • Patent number: 5959109
    Abstract: Ligand inhibitors for increasing levels of free corticotropin-releasing factor (CRF) in the brain. Such ligand inhibitors cause release of CRF from the CRF/CRF-binding protein complex. Administration of the ligand inhibitors provide improvement in learning and memory, result in decreased food intake and/or provide treatment for diseases associated with low levels of CRF in the brain, notably Alzheimer's disease.
    Type: Grant
    Filed: May 15, 1996
    Date of Patent: September 28, 1999
    Assignee: Neurocrine Biosciences, Inc.
    Inventors: Jeffrey P. Whitten, James R. McCarthy, Zhengyu Liu, Charles Q. Huang, Philip E. Erickson, Dominic P. Behan
  • Patent number: 5959444
    Abstract: A voltage generator circuit includes a first feedback transistor coupled between a supply voltage source and a first bias node, and a gate coupled to an output node. A first bias MOS transistor of a first conductivity type has a first signal terminal and a back-bias terminal coupled to the first bias node, and a gate and second signal terminal coupled to a tracking node. A second bias MOS transistor of a second conductivity type has a gate and a first signal terminal coupled to the tracking node, and a second signal terminal coupled to a second bias node. A second feedback transistor is coupled between the second bias node and a reference voltage source, and has a gate coupled to the output node. A first drive MOS transistor has a first signal terminal coupled to the supply voltage source, a gate coupled to the first bias node, and a second signal terminal coupled to the output node.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: September 28, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Stephen L. Casper
  • Patent number: 5958796
    Abstract: A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a cover layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: September 28, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Kirk Prall, Guy Blalock
  • Patent number: 5957430
    Abstract: A staple remover, with a plurality of magnets by which staples that have been removed are captured and held until they can be suitably disposed of. The staple remover has a first channel member, with a front end from which prongs extend, and a rear end and a second channel member, smaller in width than the first channel member, with a front end from which prongs extend towards the prongs of the first channel member, and a rear end pivotally attached to the rear end of the first channel member, so that the second channel member fits inside the first channel member. The channel members can move between an open position in which the prongs are separated, to a closed position in which the prongs overlap so as to grasp and remove staples from paper or other material in which they are embedded. There are supporting members attached to the channel members, with two or more magnets attached to the supporting members.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: September 28, 1999
    Inventor: Rory Olson
  • Patent number: 5959921
    Abstract: A sense amplifier that amplifies data signals in either a normal mode or an altered mode. In the normal mode, the data signals must be complementary of each other while in the altered mode, the data signals may, but need not be, complementary of each other. The sense amplifier includes two sense amplifier stages, the first of which drives the second, and each sense amplifier stage includes two identical sense amplifier circuits. A first input of each sense amplifier in the first stage receives a respective data signal, and a first input of each sense amplifier in the second stage receives an output signal from a respective sense amplifier in the first stage. In the normal mode, a mode control circuit couples each of the other data signals to a respective second input of each sense amplifier in the first stage so that the sense amplifiers receive both of the complimentary data signals at their differential inputs.
    Type: Grant
    Filed: July 24, 1997
    Date of Patent: September 28, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Chris G. Martin
  • Patent number: 5959332
    Abstract: The device has an SCR structure in a P surface zone of a silicon die. A P+ anode region for connection to an I/O terminal to be protected is formed in an N region, as well as an N+ contact region; an N+ cathode region is formed in another N region for connection to the earth of the integrated circuit. The striking potential of the SCR, that is, the intervention potential of the protection device, is determined by the reverse breakdown of the junction between the first N region and the P-body surface zone. This potential is influenced by an electrode which is disposed over the junction and is connected to the cathode constituting the gate of a cut-off N-channel MOS transistor. The concentrations are selected in a manner such that the P-channel MOS transistor defined by the P region, by the portion of the first region over which the electrode is disposed, and by the P-body, has a conduction threshold greater than the striking potential.
    Type: Grant
    Filed: August 3, 1995
    Date of Patent: September 28, 1999
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Enrico Ravanelli, Lucia Zullino
  • Patent number: 5959465
    Abstract: A method is provided for operating a programmable logic array in an integrated circuit. Each stage of the circuit is enabled only during the time necessary for that stage to propagate an incoming signal. Enable signals are generated for the stages of the circuit, using a dummy circuit which replicates elements of the circuit in dimension, orientation and connectivity. These elements provide a delay path, such that an input signal applied coincidentally to the programmable logic array circuit and the dummy circuit produces outputs of the dummy circuit which define times for applying and removing the enable signals from stages of the programmable logic array circuit.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: September 28, 1999
    Assignee: STMicroelectronics Ltd.
    Inventor: Robert Beat
  • Patent number: 5959902
    Abstract: In a first operation mode the level shifter transmits as output a logic input signal and in a second operation mode it shifts the high logic level of the input signal from a low to a high voltage. The level shifter comprises a CMOS switch and a pull-up transistor; the CMOS switch comprises an NMOS transistor and a PMOS transistor which are connected in parallel between the input and the output of the shifter and have respective control terminals connected to a first supply line at low voltage and, respectively, to a control line connected to ground in the first operation mode and to the high voltage in the second operation mode; the pull-up transistor is connected between the output of the shifter and a second supply line switchable between the low voltage and the high voltage and has a control terminal connected to the first supply line.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: September 28, 1999
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Fontana, Antonio Barcella
  • Patent number: 5957793
    Abstract: In a mechanical chain tensioner (K) which comprises a molded part having fastening openings and abutments, as a basic body (G) on which a tension bracket (B) can be mounted on the abutments, the basic body (G) is an integral molded part of filled or reinforced, injection-moldable plastic.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: September 28, 1999
    Assignee: Joh. Winkhofer & Soehne GmbH & Co.
    Inventor: Peter Schulze
  • Patent number: 5955605
    Abstract: Biotinidase-resistant biotin-DOTA conjugates, and methods of use thereof in diagnostic and therapeutic pretargeting methods are provided. These conjugates are useful in diagnosis and treatment of cancer.
    Type: Grant
    Filed: August 12, 1996
    Date of Patent: September 21, 1999
    Assignee: NeoRx Corporation
    Inventors: Donald B. Axworthy, Louis J. Theodore, Linda M. Gustavson, John M. Reno
  • Patent number: 5956715
    Abstract: A unified and straightforward approach to managing file and other resource security in a networked computing environment is disclosed. The invention can be implemented in a multi-user computer network that includes a client computer, a server computer that controls a resource sharable among users of the network, such as a shared file folder or directory, and a communications pathway between the client computer and the server computer. The resource is organized as a hierarchy of elements with a root element at the top of the hierarchy and additional elements below the root element. According to the invention, a request is received to change a protection, such as an access permission, of an element of the resource hierarchy (other than the root) with respect to a particular network user. If the element in question lacks an associated access control list, a nearest ancestor element of the hierarchy is located that has an associated access control list.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: September 21, 1999
    Assignee: Microsoft Corporation
    Inventors: Daniel S. Glasser, Ann Elizabeth McCurdy, Robert M. Price
  • Patent number: 5955919
    Abstract: An electric signal processing circuit with an operational amplifier having a signal input, a feedback input and a signal output, and a nonlinear circuit device having a characteristic with a distortion-producing nonlinearity and located in the input signal circuit or in the feedback circuit of the operational amplifier, wherein a compensating circuit device having a characteristic with generally the same nonlinearity as the characteristic of the nonlinear circuit device is disposed in the feedback circuit or in the input signal circuit of the operational amplifier for compensating the distortion of the nonlinear circuit device.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: September 21, 1999
    Assignee: SGS-Thomson Microelectronics GmbH
    Inventors: Jurgen Lubbe, Peter Kirchlechner, Jorg Schambacher
  • Patent number: D414470
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: September 28, 1999
    Assignee: Intermec IP Corp.
    Inventors: Debbie A. Chacon, John Arbak