Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs for digital signals, and an output for an analog signal. It also contains a charge integration circuit having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors corresponding to the plurality of converter inputs, the MOS transistors all having their source and drain terminals coupled together and to the input of the integration circuit, and having control terminals coupleable, under control from the plurality of inputs of digital signals, to different reference voltages having selected fixed values.

Abstract: A computer-based method and system for accessing objects of different thread types in a single process. The system provides single-threaded apartments (STAs) for loading apartment-threaded objects and a multi-threaded apartment (MTA) for loading free-threaded objects. Each STA has a single thread, and the MTA has multiple threads. When an STA thread requests to access a free-threaded object, the system creates an MTA thread and requests the MTA thread to instantiate the free-threaded object. The STA thread then receives a marshalled pointer to the free-threaded object and unmarshals the received pointer. The STA thread then accesses the free-threaded object using the unmarshalled pointer so that the MTA thread accesses the free-threaded object on behalf of the STA thread. When an MTA thread requests access to an apartment-threaded object, the system creates an STA thread and requests the STA thread to instantiate the apartment-threaded object.

Abstract: In an integrated circuit including test circuitry for testing integrated circuit function, a programmable supervoltage circuit is described for enabling the test circuitry. The supervoltage circuit includes a reference circuit, a step-down circuit, a sensing circuit, and an output circuit. The reference circuit produces a reference voltage. The step-down circuit receives an input voltage and produces a stepped-down voltage. The sensing circuit is coupled with the reference and step-down circuits, receives the reference and stepped-down voltages, and produces a sense signal as a function of the relative values of the reference and stepped-down voltages. The output circuit is coupled with the sensing circuit, receives the sense signal, and produces a supervoltage output signal to enable the test circuitry.

Abstract: The present invention is directed toward peptide analogues of human myelin basic protein for use in the treatment of multiple sclerosis. Within one aspect, peptide analogues suitable for treating multiple sclerosis are provided which are at least seven amino acids long and derived from residues 86 to 99 of human myelin basic protein. In addition, such analogues may be altered from the native sequence at positions 87, 88, 97, 98 or 99 to a D-amino acid. Additional alterations may be made at other positions. Pharmaceutical compositions containing these peptide analogues are also provided, as well as methods for treating multiple sclerosis.

Abstract: Compositions and methods are provided for the treatment of diseases associated with mitogen activated protein kinase cascades. In particular, the mitogen-activated protein kinase p38-2, and polypeptide variants thereof that stimulate phosphorylation and activation of substrates such as ATF2, are provided. The polypeptides may be used, for example, to identify antibodies and other agents that inhibit or activate signal transduction via the p38-2 kinase cascade. Such polypeptides and agents may also be used for the treatment of diseases associated with mitogen-activated protein kinase cascades.

Abstract: A memory device includes an array of memory cells arranged in rows and columns. A row-address decoder allows a row address to propagate therethrough while a row address strobe is at an inactive logic level. In response to a transition of the row address strobe from the inactive level to an active level, the decoder enables a row of memory cells selected by the row address. A row-address latch stores the row address in response to the transition of the row address strobe. The memory device may also include a transition detector that monitors the row address for a transition thereof. A delay circuit is coupled to the decoder, the latch, and the detector. If the monitor detects a transition of the row address, the delay circuit delays the enabling of the row of memory cells and the storing of the row address at least predetermined time after such a transition.

Abstract: A method of fabricating bipolar junction transistors particularly suitable for electrostatic discharge protection and high voltage MOSFETs. In accordance with the invention, a mask covers bird's beaks formed between field oxide layers and doped regions of a semiconductor substrate. A silicide layer is then added to the exposed surface of the doped regions. The mask prevents the silicide layer from overlying the bird's beaks, thereby precluding the silicide layer from degrading the breakdown junction voltage of the transistor.

Abstract: A field emission display includes a discrete storage capacitor coupled between a row line and a reference potential. The display also includes a discharge circuit coupled between a transmission line tap and the storage capacitor. The discharge circuit receives a pulsed image signal from the transmission line and transfers charge from the transmission line to the storage capacitor. In one embodiment, the discharge circuit includes a pair of opposed zener diodes. In response to a brief negative-going input pulse on the transmission line, the capacitor is discharged through the diodes. Then, the diodes recover and capacitor and row line are isolated from the tap. A selected line of an extraction grid is activated to cause an emitter set coupled to the row line to emit electrons. The emitted electrons are replaced by electrons from the capacitor. The capacitor has sufficient capacitance to supply electrons over an expected refresh interval of the row line.

Abstract: A simulated weapon includes a pressure switch within the simulated weapon's barrel. The pressure switch responds to pressure changes within the weapon barrel to activate a light emitter. In response, the light emitter emits a beam of light that simulates weapon fire by indicating the aim of the simulated weapon. Pressure changes within the barrel are induced by a conventional air cartridge that emits a blast of air when struck by the firing pin of the simulated weapon. The user can thus produce the simulated fire by activating the simulated weapon's trigger to trip the hammer and drive the firing pin into the air cartridge. In another embodiment, the simulated weapon activates a nonlethal pyrotechnic round. Simulated fire is produced in response to detection of the recoil, force, or pressure change produced by the pyrotechnic round. The simulated weapon may be a pistol, rifle or any other conventional hand held weapon.

Abstract: An output driver circuit offers wave-shaping and logic level adjustment for high speed data communications in a synchronous memory such as a dynamic random access memory (DRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Wave-shaping functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtains different wave-shaping characteristics of the output signal.

Abstract: Mammalian Asx gene and amino acid sequences encoded by the mammalian Asx gene, are described. The mammalian Asx gene and gene products are useful for diagnostic and therapeutic applications in proliferative and developmental disorders. Modulators of mammalian Asx can be identified using the disclosed genes. The modulators can be used in the context of cancer therapy or a treatment of a developmental disorder. Asx is also useful for inducing differentiation in a population of progenitor cells.

Abstract: A method of manufacturing surface relief holograms wherein an original surface relief hologram in the form of an endless loop or a drum is continuously coated with a radiation-curable resin. After curing, the resin bears a replica of the original hologram and it is continuously drawn off from the original as a sheet or film. The replica film becomes a hot-stamping foil when formed in contact with a carrier film, metallized, and coated with a hot-stamping adhesive.

Abstract: A bread making machine having an automated dispenser unit and a pause function is described. The automated dispenser unit is integrated within a chamber lid covering a bread making chamber in which bread making ingredients are mixed, kneaded, and baked. The automated dispenser accepts certain ingredients, such as fruit and/or nuts, which are automatically added to the bread making chamber after significant processing of other ingredients in the bread making chamber has occurred. The automatic dispenser unit includes a dispenser door adjacent to the bread making chamber. The dispenser door is held in a closed position by a latch assembly. The latch assembly is mechanically linked to a solenoid core, which moves in response to a control signal issued by electronic control circuitry, causing the dispenser door to open. The bread making machine includes a pause function, which allows a user to temporarily suspend the bread making operation at any time, by pressing a pause key on a user interface keyboard.

Abstract: A computer system and method process memory requests for access to a computer memory. The computer system arbitrates between current memory requests based on an immediately previous memory request that was most recently selected for transmission to the memory. The computer system minimizes the number of read/write delays by selecting one of the current memory requests based on the request types (read or write) of the current memory requests and the immediately previous memory requests. The number of RAS/CAS delays are reduced by selecting one of the current memory requests based on whether any of the rows to which the current memory requests are directed matches the row to which the immediately previous memory request was directed. The number of pre-charge delays is reduced by selecting one of the current memory requests based on whether any of the current memory requests is directed to a memory bank other than the memory bank to which the immediately previous memory request was directed.

Abstract: A method and system for sharing application programs between multiple computer systems. In one embodiment, the present invention comprises a multipoint application sharing (MAS) system that resides at each computer system (i.e., node) in a network of computer systems. The MAS system at each computer system communicates with each MAS system at each other computer system by sending messages over the network. The MAS system enables a user at each computer system to share one or more application programs with each user at each other computer system. To share an application program, a user at a host computer system invokes the application program. Then, the user requests the MAS system to share the invoked application program with users at other computer systems. Each computer that is sharing the application, can view the output of the application and can, under certain circumstances, take control of the application so that it can send remote keyboard and pointing device information to the application.

Abstract: A memory array is divided, at the design stage, into a plurality of elementary sectors; depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors of desired size and number; a correlating unit memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address is supplied to the correlating unit which provides for addressing the elementary sectors associated with the addressed composite sector on the basis of the memorized correlation table.

Abstract: A current controlled matrix addressable display includes a charging transistor, a driving transistor and a switching transistor that control current flow to a light-emitting assembly. The control circuit is driven by a row signal, a column signal and a clocking signal. The column signal is a combination of an image component and a pulsed charging component. The image component establishes a gate voltage that is trapped at the gate of the charging transistor by the switching transistor in response to the row signal. The clocking signal and the charging component form pulse pairs that transfer charge from a column line to a common node and then from the common node to the light-emitting assembly. The intensity of light is controlled by the voltage difference between the image component and the voltage of the clocking signal. Additionally, the intensity of emitted light can be controlled by controlling the number of pulse pairs in a return interval during which the pulse pairs arrive.

Abstract: An electromechanical dental flossing device is disclosed for flossing the area between a portion of the tooth and the gum tissue. The device comprises an elongated member coupled to a motor source to effect oscillation of the elongated member. The elongated member includes an intermediate portion and a tip which are capable of being received between the tooth and the gum tissue.

Abstract: A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the variable delay line produces a delayed output clock signal that is compared at a race detection circuit to the input clock signal. If the delayed clock signal leads the input clock signal, the race detection circuit increments a counter that controls the binary-coupled capacitors. The incremented counter increases the capacitance by coupling additional capacitance to the variable delay line to delay propagation of the delayed clock signal. If the delayed clock signal lags the original clock signal, the race detection circuit decrements the counter to decrease the capacitance, thereby decreasing the delay of the variable delay line.

Abstract: The device comprises a first chain of scanning cells located at the stimulation input of each respective functional block of the integrated circuit and a second chain of scanning cells located at the assessment output of each respective functional block of the integrated circuit. Each cell comprises a master part, a slave part and switching circuit to alternately enable the master and slave parts under the control of respective master clock and slave clock signals coincident with opposite phases of a scanning clock signal having a substantially square wave. With each pair of chains of scanning cells there are associated clock generators to locally obtain the master and slave clocks from the scanning clock.