Abstract: An ID administration tool includes a request for service (RFS) database, including an approval queue and an error queue. An ID creation database includes registration code, an approved requests file, and a profile documents. A plurality of requests for new user IDs are received into the RFS database, queued in the approval queue, moved to the approved requests file where they are sorted by profile and processed in profile groups to generate the new user IDs.

Abstract: A client IP address is communicated to server applications in a secure Telnet client/server system. During a client/server session, the terminal type is first negotiated, followed by negotiation of environment options, including requesting and receiving the client IP address. Upon creating a virtual device for the session, the client address in stored in device associated space in sockaddr_in format where it becomes available to the server applications through the QDCDEVD API.

Abstract: A computer program receives a large plurality of module design parameters and provides as output a graphical representation of the design together with text files that rate module wireability, including die pad position, attachment of each die pad to its BGA pad, and net cross-over; summarizes input parameters; creates a truth table for rating wireability and thermal requirements; provides cost sensitive parameters such as gold area, drill size and number requirements.

Abstract: System and method for serving HTML pages to web browsers for the purpose of administration and configuration. A plurality of instances of WWW servers is provided, with one such instance including a configuration file which is restricted in usage and not alterable by way of any HTML configuration or administration forms. This plurality of instances of internet connection servers is managed by way of a web browser which displays and interacts with a plurality of HTML forms and corresponding common gateway interface binary programs which are provided selectively for creating and deleting instances of servers, associating a configuration file with a server instance, changing server instance start up parameters, and starting, ending, and restarting server instances.

Abstract: A host system and a local system (work station) comprise a system for updating source code. The host system includes a compiler and any necessary tools for compilation of source code which is characterized by, for example, database statements. While the work station also includes a compiler, it lacks tools for translating the database statements. Consequently, the host system expands and marks the original source to create a marked expanded source file which is in a form compilable at work station without the tools. The work station then modifies the source file, and returns a processed source file to the host system, where the marking and preprocessing are undone and the source file returned to its original form (but now as changed by the work station).

Abstract: A memory controller used to manage the memory interface (main store interface) for processor and input and output (I/O) device access, includes a trace array used for accumulating trace data signals to be stored to main store, control logic used to determine when the array should be updated and when its contents should be stored to main store, an address register which provides the starting address of main store assigned to store trace data, an offset address register which identifies the current address to store trace data, and a space size register used to identify the amount of main store reserved to store trace data. In a first implementation, the contents of the trace array are moved to main store when the trace array becomes full. An alternative implementation provides additional control registers and logic which allow memory to be updated from the trace array when the memory interface is not busy.

Abstract: A plurality of parallel execution units are selectively powered from a plurality of power sources, the power to each execution unit being selected based upon expected time to completion of processing within the execution unit. Maximum power is gated to execution units executing complex instructions, or time-critical instructions. Less than maximum power is gated to execution units executing simple instructions, or instructions which are not time-critical, or in response to pipeline hazards or stalls. When less than maximum power is gated to an execution unit, a step up circuit may be employed to raise the output of that execution unit to maximum power.

Abstract: Tasks make updates requested by calling tasks to a shared resource serially in a first come first served manner, atomically, but not necessarily synchronously, such that a current task holding an exclusive lock on the shared resource makes the updates on behalf of one or more calling tasks queued on the lock. Updates waiting in a queue on the lock to the shared resource may be made while the lock is held, and others deferred for post processing after the lock is released. Some update requests may also, at the calling application's option, be executed synchronously. Provision is made for nested asynchronous locking. Data structures (wait_elements) describing update requests may queued in a wait queue for update requests awaiting execution by a current task, other than the calling task, currently holding an exclusive lock on the shared resource.

Abstract: An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.

Abstract: A memory coherency controller. Responsive to a request including a request type and request memory address, relevant queues are examined for queued addresses matching the request memory address. Responsive to a request memory address matching at least one of the queued addresses, the request is rejected. Following a retry latency, the request is retried. When the address of a read request matches queued address in a store queue, at least one request in the store queue is prioritized higher than all other queued requests.

Abstract: A computer system allocates processor time to multiple users. A systems operator or other administrator specifies to the computer a share of processor time for each user. A particular user's CPU usage is limited to an absolute value in a ‘dispatch driven’ multiprocessing system through the use of a monitor built into an active wait routine. The mechanism used is a list of users whose CPU resource must be limited so that their consumption does not exceed the limit value. The limit list is active wait monitored to determine when a user should be removed from the list in a low load situation and thus deliver the maximum CPU usage to the user if it is available.

Abstract: A cache system is provided for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. A two level cache subsystem including an L1 cache and an L2 cache is provided. A cache directory is accessed for a second snoop request while a directory access from a first snoop request is being evaluated. During a REQUEST stage, a directory access snoop to the directory of the L1 cache is requested; and responsive thereto, during a SNOOP stage, the directory is accessed; during an ACCESS stage, the cache arrays are accessed while processing results from the SNOOP stage. If multiple data transfers are required out of the L1 cache, a pipeline hold is issued to the REQUEST and SNOOP stages, and the ACCESS stage is repeated. During a FLUSH stage, cache data read from the L1 cache during the ACCESS stage is sent to the L2 cache.

Abstract: A programmable timing circuit on an integrated circuit chip for testing the cycle time of functional circuits on the chip. The timing circuit includes a selectable input having at least two sources, one of which is a toggle circuit; a minimally delayed control path including a control latch; a programmable delay path in parallel with the control path and including a sample latch; and a comparator for comparing the state of the control latch and sample latches to provide a signal indicative of the delay path being longer than the control path. A plurality of configuration latches and multiplexers are provided for selecting the input source and routing an input signal through specific delay blocks to control the amount of delay in the delay path.

Abstract: A communications apparatus is provided comprising a plurality of FIFO buffers, each with independent control and priority logic under software control for supporting different types of message traffic, both send and receive, such as comprise a multimedia server system. Processor software directs messages to specific, optimized FIFO buffers. Further, a system is provided including a plurality of nodes wherein a sending node specifies the communications path through the system, selecting specific FIFO buffers in each node for buffering its messages.

Abstract: An administration server system and method which is capable of managing multiple copies or instances of servers includes an administration server; an administration server instance file; an administration server read-only configuration file for storing configuration directives; an administration server read-write configuration file for storing configuration directives; a services table; a rules list; and a worker thread pool.

Abstract: A network adapter capable of adapting its transmission speed to that of another adapter of the same or slower speed so as to mix adapters of different speeds in the same communication network. In send mode, the adapter selects one of a plurality of transmission speeds based on the message header including a field specifying the message speed, which speed is known to be supported by the adapter at the addressed receive node. The sending adapter prefixes the message with a synchronization byte which defines transmission speed selected and transmits the message at the selected speed. In receive mode, the adapter decodes within one clock cycle the message speed from the message synchronization byte, and responsive thereto generates the clock for gating the receive message into adapter memory.

Abstract: An extensible framework provides a unified interface for data manipulation in a dynamic object-based format. A data access layer of the Transmission Control Protocol/Internet Protocol (TCP/IP) Graphical User Interface (GUI) component uses ODBC to read and write files. Four abstractions implement the framework. These are (1) a CDatabaseManager class that provides access to data stored in a database; (2) a CSpecializedFile class which composes a CDatabaseManager that abstracts the management of reading and writing to database files and provides a unified interface for use by accessors.

Abstract: In an Internet system having a plurality of applications, and a plurality of servers for attachment from a plurality of web browsers, a system supports connection oriented applications over a connectionless protocol. At least one of the servers is a master server work station gateway owning a well-known port, and the other servers are slave servers supporting established web browser-to-application state sessions. Dynamic session authentication checking is done by the server to prevent the occurrence of screen spoofing by providing authentication keys which are unique to each session and each panel.

Abstract: In an Internet system having a plurality of applications, and a plurality of servers for attachment from a plurality of web browsers, a system supports connection oriented applications over a connectionless protocol. At least one of the servers is a master server work station gateway owning a well-known port, and the other servers are slave servers supporting established web browser-to-application state sessions. Dynamic session authentication checking is done by the server to prevent the occurrence of screen spoofing by providing authentication keys which are unique to each session and each panel.

Abstract: A shared memory parallel processing system interconnected by a multi-stage network combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller and network adapter, which implements three send FIFOs and three receive FIFOs at each node to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.