Abstract: A data model for abstracting customer-defined VPN security policy information. By employing this model, a VPN node (computer system existing in a Virtual Private Network) can gather policy configuration information for itself through a GUY, or some distributed policy source, store this information in a system-defined database, and use this information to dynamically negotiate, create, delete, and maintain secure connections at the IP level with other VPN nodes.

Abstract: System control of compression and decompression of data based upon system aging parameters, such that compressed data becomes a system managed resource with a distinct place in the system storage hierarchy. Processor registers are backed by cache, which is backed by main storage, which is backed by decompressed disk storage, which is backed by compressed disk storage then tape, and so forth. Data is moved from decompressed to compressed form and migrated through the storage hierarchy under system control according to a data life cycle based on system aging parameters or, optionally, on demand: data is initially created and stored; the data is compressed at a later time under system control; when the data is accessed, it is decompressed on demand by segment; at some later time, the data is again compressed under system control until next reference. Large data objects are segmented and compression is applied to more infrequently used data.

Abstract: System and method for controlling the contents of a browser cache. A data stream from a host server to a client browser includes a clear cache tag. Responsive to the clear cache tag, the browser clears its cache. The data stream may also include a start cache tag, and one or more data files which are cached by the client browser. Responsive to the clear cache tag, the browser cache is cleared of data files received in the data stream between the start cache tag and the clear cache tag, or alternatively of all data files in cache associated with a cache identifier received in the start cache and clear cache tags. Either the client local file system or a field in a cache table is used to differentiate between successive start cache tags.

Abstract: A graphical user interface includes a buddy dialog which dynamically becomes part of a current dialog upon selection of a selectable object on a property page. A unique buddy dialog format is provided for each of a plurality of data formats for selectable options, or objects, displayed on the property page. The user may see the values for each of several associated options by clicking (or otherwise selecting) on each option successively. Each time an option is selected, its data values appear in its corresponding buddy dialog without popping up another dialog.

Abstract: A method and system for representing business processes such as in a workflow model. Each of a plurality of processes is defined as a 3-tuple including a noun, a verb and an attribute, and a selected process is displayed as a point in navigation space. In this manner, business processes are classified and organized in terms of a 3-dimensional process navigation space facilitating process identification, decomposition and definition by traversal of this space.

Abstract: An interface apparatus includes a base element, an interface element, and an attachment mechanism for attaching the interface element to the base element. The attachment mechanism is pivotable within a plurality of degrees of freedom. The interface element is an extensible member which is, in two of its embodiments, pivotally mounted so as to be rotatably adjustable about a pivot point with respect to a primary member. The primary member may be a base member or another display member. These members may be computer keyboards or displays, such as liquid crystal displays (LCDs), audio speakers, or the like such as are used in desk top or lap top computers and terminals.

Abstract: Rapid toggling of application windows to the forefront of a computer monitor. One or more queues are established by a user comprising indicia representative of a sequence of a plurality of open application windows. Sequential toggling among the windows of a given sequence is accomplished by actuating a mouse pointer positioned to the white space of any window within the given sequence.

Abstract: A storage controller, upon detecting an interval of storage inactivity, inhibits external storage refresh commands and places the storage in self timed refresh (STR) mode. Upon detecting storage activity while storage is in STR mode, the controller terminates STR mode in storage. Upon detecting a scrub request while storage is in STR mode, the controller terminates STR mode in the storage and thereafter services the scrub request. Upon completing execution of the scrub request, the controller returns storage to STR mode.

Abstract: System and method for scheduling I/O requests in a multi-tasking data processing environment. An I/O request issued by an application is placed in an I/O request holding queue. Under control of the requesting application (or, alternatively, the operating system), the I/O request is selectively canceled or moved to a service pending queue for execution. Requests can be moved either by the application or by the Operating system when an I/O completes (and hence the service pending queue has room for another IO).

Abstract: A plurality of parallel execution units are selectively powered from a plurality of power sources, the power to each execution unit being selected based upon expected time to completion of processing within the execution unit. Maximum power is gated to execution units executing complex instructions, or time-critical instructions. Less than maximum power is gated to execution units executing simple instructions, or instructions which are not time-critical, or in response to pipeline hazards or stalls. When less than maximum power is gated to an execution unit, a step up circuit may be employed to raise the output of that execution unit to maximum power.

Abstract: An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.

Abstract: A system and method for porting a multi-threaded program to a job model. Data that needs to be shared between different jobs is globalized by storing data in a user space accessible to all of the jobs. Thread controls are replaced by job controls by replacing thread function calls by job commands wrappered to appear as functions.

Abstract: Chip carrier topology including a plurality of bond lines radiating from a line of chip pads to at least one of zero or more finger lines and zero or more voltage lines is defined by first collecting topology parameters selected from the set including the number of rows of fingers; the spacing between rows of fingers; finger style, said finger style being one of arc-of-circle, constant-bond-length, and encompassing-rectangle; location of voltage rings; value of voltage rings; location of chip pads; voltage of chip pads; dimensions of output fingers; minimum finger pair spacing; maximum finger angle with respect to its bond line; minimum spacing of bond line terminations at voltage rings; and minimum spacing of bond line terminations with respect to and adjacent bond line which terminates at a finger. A plurality of possible topology solutions are generated, and a single possible topology solution selected for further processing.

Abstract: IP network address translation (NAT) and IP filtering with dynamic address resolution in an Internet gateway system. Symbolic interface names are recognized in selected rule statements. An symbolic s-rule file is generated from these rule statements which includes symbolic interface names. During processing of a packet message, the s-rule file corresponding to the interface name in the packet message is processed, with symbolic addresses in the s-rule file resolved to the IP addresses obtained from the packet message.

Abstract: An apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. The apparatus is relatively easy to implement and inexpensive to build. The communication media is switch-based and is fully parallel, supporting nodes interconnected by the switching network.

Abstract: A method and apparatus is provided for assuring balanced servicing of interrupts among devices at the same interrupt level in a daisy-chain architected bus, such as the VME bus, by detecting that a second device on the same level as a first device is having an interrupt serviced, and responsive thereto raising the interrupt level of the first device.

Abstract: Contention losses are minimized in path searching, circuit-switched networks by adding intelligence to the last stage of the network. A count of number of bytes remaining to be transferred in each active message is maintained in real time for each output port of the network. If contention arises at the last stage switch being requested in camp-on mode to make a connection to a busy output port, the switch checks the bytes remaining count and responds differently depending on how the bytes remaining count compares to a preset threshold register. If the count remaining is below the threshold, the last stage switch accepts the camp-on request, because the desired output port will be available shortly. If the count remaining is above the threshold or below the threshold but another user is camped-on, the switch rejects the camp-on request to the last stage, because the desired output port will not be available shortly. In this case further path searching would be meaningless.

Abstract: A memory coherency controller. Responsive to a request including a request type and request memory address, relevant queues are examined for queued addresses matching the request memory address. Responsive to a request memory address matching at least one of the queued addresses, the request is rejected. Following a retry latency, the request is retried. When the address of a read request matches queued address in a store queue, at least one request in the store queue is prioritized higher than all other queued requests.

Abstract: A system and method for managing access by a user to a reusable resource. An integer pool is provided, along with program and hardware structures for obtaining an integer from the integer pool, for returning an integer to the integer pool. Responsive to the integer pool being empty, the user is waited. The integer pool includes a NEXT control structure from which a next integer is obtained for use and into which an integer is loaded upon being made available for reuse. The integer pool includes, for holding integers received from or to be provided to said NEXT control structure, (a) a LIFO stack or (b) a linked list by proxy. Reusable resources include data buffers, hardware status bits, logical connections and/or data channels.

Abstract: A programmable timing circuit on an integrated circuit chip for testing the cycle time of functional circuits on the chip. The timing circuit includes a selectable input having at least two sources, one of which is a toggle circuit; a minimally delayed control path including a control latch; a programmable delay path in parallel with the control path and including a sample latch; and a comparator for comparing the state of the control latch and sample latches to provide a signal indicative of the delay path being longer than the control path. A plurality of configuration latches and multiplexers are provided for selecting the input source and routing an input signal through specific delay blocks to control the amount of delay in the delay path.