Abstract: A power supply apparatus and method for an active matrix organic light emitting diode (AMOLED) is disclosed. The power supply apparatus supplies power to the AMOLED while using a switching frequency varied in accordance with a clock signal, and includes a load checker for comparing a load current of the AMOLED with a first reference voltage, and outputs a result of the comparison as a load check signal, and a frequency oscillator for generating the clock signal which has a variable frequency in response to the load check signal. The power supply apparatus is switched in accordance with a clock signal having a frequency modulated based on a load condition of the AMOLED, for example, a load current. Accordingly, it is possible to reduce switching power loss caused by unnecessary power consumption under the condition that a small load current is generated, thereby achieving an enhancement in efficiency.

Abstract: Disclosed is an apparatus for analyzing pulse using an array of pressure sensors comprising: an array of pressure sensors that measures the pulse data with a plurality of piezoresistive pressure sensors; a moving part that moves the array of pressure sensors; a controller that controls the moving part, so that the array of pressure sensors can be positioned at the pulse diagnosis site, and analyzes the pulse data measured by the array of pressure sensors; and a display that displays the pulse profile analyzed by the controller. Since both the applied pressure and the pulse pressure can be measured simultaneously using the piezoresistive pressure sensors, various pulse diagnosis techniques can be applied and since pulse length, pulse thickness, etc. can be displayed in four dimensions, softness or roughness of the pulse and other pulse information can be conveyed visually.

Abstract: An EEPROM device may have, at the region where the control gate is formed, a gate oxide layer having a relatively smaller thickness than the gate oxide layer of the tunneling region by removing the gate oxide layer, at a predetermined thickness, at the region where the control gate is formed. Thus, integration of an EEPROM device may be maximized as a result of minimizing the area of the control gate.

Abstract: A portable safety ladder assembly having safety extensions to permit safe and easy access to landing areas, working platforms, scaffolds, etc. The safety extension members have a plurality of horizontal handgrips ergonomically designed to prevent falls from the ladder assembly when a user is ascending upward or descending downward thereon.

Abstract: A scheduling method for a wireless communication system is disclosed. The method includes (a) selecting n(<N) terminals among the N terminals included in the wireless communication system; (b) receiving channel state information from the selected terminals and allocating wireless resources to at least one terminal among the selected terminals; (c) performing transmission or reception via the allocated wireless resource at the at least one terminal; and (d) newly selecting n terminals and returning to the (b) step, wherein the remaining terminals except for the selected terminals inactivate the transmitting and receiving function at the steps of (b) and (c). Therefore, a wireless cellular network adapted to improve the energy efficiency in fairness is provided.

Abstract: A source driver and a liquid crystal display (LCD) device having the same. A source driver may carry a clock in a data current, and may recover a clock signal and/or a data signal without being substantially affected by external frequencies and/or resistance. A source driver may include a trans-impedance amplifier which may receive data currents, convert data currents into voltages, and/or output voltages as data voltages and/or clock voltages. A source driver may include a comparator electrically coupled to a trans-impedance amplifier, which may change levels of data and/or clock voltages applied from a trans-impedance amplifier, and/or may output level-changed voltages as data signals and/or a clock signal.

Abstract: A stable and reliable EEPROM device includes an EEPROM cell having first, second and third control voltage terminals for performing operations for programming, reading and erasing data, respectively, a first transistor configured to supply a programming operation voltage to the first control voltage terminal during the programming operation, a second transistor configured to supply a ground voltage to the first control voltage terminal, the data of which will not be programmed during the programming operation, and a third transistor connected to the second control voltage terminal and turned on by an address selected for reading the data of the EEPROM cell during the reading operation.

Abstract: A low power frequency divider and a low power phase locked loop, which consume the least power. The low power frequency divider generates a frequency dividing signal by dividing a frequency of an input signal in a uniform ratio, and includes a phase to voltage converter, a comparator, a phase synchronization circuit, and a reset circuit. The phase to voltage converter generates a phase voltage signal corresponding to phase change of the input signal in response to a reset signal. The comparator generates a comparator signal by comparing the phase voltage signal and a reference phase voltage signal. The phase synchronization circuit generates the frequency dividing signal by matching phases of the input signal and the comparator signal. The reset circuit generates the reset signal in response to the comparator signal or the frequency dividing signal.

Abstract: An apparatus and method for measuring the characteristics of a semiconductor device is disclosed. The measuring apparatus may include first to M-th (wherein M is a positive integer not less than 1) starved devices each being biased in response to a bias voltage varying in accordance with a variable first supply voltage, thereby varying an amount of current flowing through a semiconductor device included in the starved device. Interconnect lines may interconnect the first to M-th starved devices. A measuring unit measures at least one of a delay time caused by the semiconductor devices of the starved devices themselves, and a compound delay time caused by the semiconductor devices of the starved devices themselves plus a delay time caused by the interconnect lines. The measured results can be analyzed under conditions more approximate to diverse situations exhibited in practical chips in accordance with development of manufacturing processes and techniques.

Abstract: An optofluidic lithography system including a membrane, a microfluidic channel, and a pneumatic chamber is provided. The membrane may be positioned between a pneumatic chamber and a microfluidic channel. The microfluidic channel may have a height corresponding to a displacement of the membrane and have a fluid flowing therein, the fluid being cured by light irradiated from the bottom to form a microstructure. The pneumatic chamber may induce the displacement of the membrane depending on an internal atmospheric pressure thereof.

Abstract: An address assignment method of a mobile node, for hierarchical routing in a low-power wireless personal area network (LoWPAN), includes (a) classifying a plurality of fixed nodes in a hierarchical way, (b) designating a management node and a head node of a lower level than the level of the management node in the fixed nodes, (c) determining if the mobile node can communicate with the head node, and (d) assigning an address to the mobile node through a neighboring head node, which can communicate with the mobile node when the mobile node cannot communicate with the head node. Therefore, addresses may be assigned without limitation until the addresses for the mobile nodes are exhausted. Furthermore, even when the mobile node having an assigned address from a first region moves from the first region to a second region, the packet may be sent or received through the hierarchical routing.

Abstract: Embodiments relate to a manufacturing method of a one time programmable (OTP) memory device including: forming a common source in a linear configuration on a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate at both sides of the source; forming a gate over the gate dielectric layer; forming a spacer between the gates and at both side walls of the gate; and forming a drain on the semiconductor substrate at both sides of the spacer. With embodiments, the OTP memory device can be formed together with the logic part using the logic process and can increase the storage capacity of the OTP memory device by improving density of memory arrays.

Abstract: A micro coaxial cable with a high bending performance, having an inner conductor; an insulating layer configured to surround the inner conductor, and a helical winding conductor configured to surround the insulating layer and having an elongation of 1.5 to 4% and a pitch of 3.0 to 5.0 mm.

Abstract: A router connects an Internet protocol (IP)-ubiquitous sensor network (USN) with an external network. The IP-USN is disclosed when the IP-USN includes one or more routers. An IP-USN with multiple routers includes one or more routers, and sensor nodes in the IP-USN may reliably communicate with the external network. The sensor nodes in the IP-USN may communicate with one another using the router if necessary. When one router does not operate, communication with the external network is performed by using other routers.

Abstract: Provided is a V-groove processing apparatus for cutting and V-groove processing. The V-groove processing apparatus includes a processing unit for processing V-grooves in an engineered stone raw plate fixed on a table while being transferred by a transfer unit. Here, the processing unit includes a circular saw blade disposed at a front of a cutting panel to cut the engineered stone raw plate, one or more cutters disposed on a front of a cutter housing to form a V-groove inside a cut surface, a first rise and fall unit transferring the circular saw blade to a cutting location during the cutting of the engineered stone raw plate and restoring the circular saw blade to an original place after the cutting of the engineered stone raw plate, and a second rise and fall unit transferring the circular saw blade and the cutters to a V-groove forming location during the formation of the V-groove and restoring the circular saw blade and the cutters to original places after the formation of the V-groove.

Abstract: A semiconductor device includes a semiconductor substrate including a CMOS region and a bipolar region, a first N well and a first P well in the CMOS region, a PMOS device in the first N well and an NMOS device in the first P well, a deep P well in the bipolar region, a second N well in the deep P, a second isolation layer between the deep P well and the second N well, a third isolation in the second N well, a collector in the second N well between the second and third isolation layers, and a base formed in the second N well and having a bottom surface including first type impurities to contact the emitter.

Abstract: A semiconductor device includes an isolation layer formed on and/or over a semiconductor substrate to define an isolation layer, a drift area formed in an active area separated by the isolation layer, a pad nitride layer pattern formed in a form of a plate on the drift area, and a gate electrode having step difference between lateral sides thereof due to the pad nitride layer pattern.

Abstract: Technology for a wireless multi-hop network is provided. A method by which a source node operates in a wireless multi-hop network includes selecting one of first to M-th frame structures (M is a natural number greater than or equal to 2), based on a data packet generation interval, when the source node is in an active state, synchronizing with neighboring nodes in a first synchronization period of the selected frame structure, and when the source node is in the active state, transmitting a control packet to a next hop in a data period of the selected frame structure, and waiting for a response from the next hop, the control packet indicating that the source node will transmit a data packet in a sleep period subsequent to the data period and including information on the selected frame structure. Here, each of the first to M-th frame structures defines a frame including at least one synchronization period, at least one data period, and at least one sleep period, and having a different duty cycle.

Abstract: A semiconductor device includes a semiconductor substrate in which a first trench is formed and a second trench is formed at the middle portions of the first trench; and a first ion implantation layer that is formed on the surface of the semiconductor substrate and on the bottom of the first trench, the portions formed on the bottom of the first trench being spaced from each other by the second trench. A gate is formed from the bottom of the both side walls of the first trench to the middle portions thereof; a drift region is formed at both side walls of the first trench over the second trench; and a second ion implantation layer formed on the inner surface of the second trench.