Abstract: An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.

Abstract: An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors. Each BC routing channel is coupled to an expressway tab to provide access for each B1 block to the expressway routing channels M1, M2, and M3, respectively.

Abstract: A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1+/?0.4, and the ratio of x to y in SixNy is in a range of about 0.75+/?0.225.

Abstract: A firewall for authenticating a user access request is disclosed. The firewall device may include a proxy process for processing incoming connection requests. The proxy is configured to receive an access request from a user over a first communication medium and prompt the user for a username and a first password portion over the first communication medium. The firewall may then send a second password portion to the user over a communication medium other than said first communication medium responsive to receiving a valid user name and first password portion pair from the user. The firewall may then verify the access request responsive to receiving the second password portion from the user through the first communication medium. The firewall may send passwords to a mobile device for verification.

Abstract: An integrated circuit system includes a first integrated circuit die and a family of second integrated circuit dice. The first integrated circuit die have input/output circuits disposed thereon and further have a first array of face-to-face bonding structures disposed on a first face thereof. Each member of the family of second integrated circuit dice have logical function circuits disposed thereon and further have a second array of face-to-face bonding structures disposed on a first face thereof. The second array of face-to-face bonding structures of each member of the family mates with a different portion of the first array of face-to-face bonding structures.

Abstract: An integrated circuit device has a state-saving feature and includes a programmable logic block, I/O pads, a dedicated register, at least one volatile memory block, a non-volatile memory block, a condition-sensing circuit for detecting at least one condition, A control circuit such as a state machine controls the saving of states of various volatile memories and registers to the non-volatile memory and also controls the initialization of the volatile registers and memories using the saved state data.

Abstract: A surfboard for use by riders on bodies of water is disclosed having first and second apertures extending through the surfboard from the bottom side to the top side, angled such that each aperture has a first opening on the bottom side and extends at an angle toward the tail end of the surfboard to a second opening on the top side of the surfboard. A first channel disposed within a portion of the bottom side of the surfboard, terminating at the first opening of the first aperture, and a second channel disposed within a portion of the bottom side of the surfboard, and terminating at the first opening of the second aperture, the first channel and second channel separated by a raised portion of the bottom side, thus defining a trimeran profile on the bottom side, the trimeran profile having a first and second rail, and a center portion.

Abstract: A method for manufacturing an emulsifier package is disclosed. The method comprises blending a flow of fuel soluble product, a flow of stabilizer, and a flow of water in a mixing vessel to form a mixture. Mixing the mixture in the mixing vessel and recirculating the mixture through the mixing vessel. Lastly, shearing the mixture with a shearing device at a rate of about 27,500 shears per second to about 87,500 shears per second. A method for manufacturing an aqueous fuel emulsion is also disclosed.

Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

Abstract: A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current flowing in the bit line. The output voltage of the current-to-voltage converter is compared to a reference voltage derived from the output of a reference current-to-voltage converter whose input is driven by a reference current on a reference bit line. Any cell that conducts more current than the reference current will be regarded as an erased cell. Conversely, any cell that conducts less current than the reference current will be regarded as a programmed cell.

Abstract: A garment stretching device comprising: a top T-member defined by a horizontal member and a vertical member, the vertical member having a plurality of notches longitudinally disposed along its surface; a top L-member defined by a horizontal member and a vertical member, the horizontal member and the vertical member each having a plurality of notches longitudinally disposed along their surface; a first bottom member defined by a top horizontal member, a vertical member, and a bottom horizontal member; a second bottom member defined by a top horizontal member, a vertical member, and a bottom horizontal member, the top horizontal member and the bottom horizontal member each having a plurality of notches longitudinally disposed along their surface, wherein the top T-member, the top L-member, the first bottom member, and the second bottom member are configured to adjustably interlock using the pluralities of notches in conjunction with corresponding locking mechanisms.

Abstract: A method for detecting encoded digital data from a substantially sinusoidal waveform, the encoded digital data having one of a first value and a second value at selected phase angles ?n comprises generating the waveform having an amplitude Y defined by a first function at phase angles lying outside of regions having a range ?? beginning at each phase angle ?n, said first function being Y=sin ?; generating the waveform having an amplitude Y defined by the first function at phase angles lying inside the regions having a range of ?? beginning at each phase angle ?n where data of the first value is to be encoded; and generating the waveform having an amplitude Y defined by a second function at phase angles lying inside the regions having a range of ?? associated with each phase angle ?n where data of the second value is to be encoded, the second function being different from Y=sin ?, the detection including deriving sync pulses from minima and maxima of the substantially sinusoidal waveform to frame data words.

Abstract: Method and system for efficiently handling hub and spoke area topologies in a data network under Open Shortest Path First (OSPF) routing protocol which provides selective blocking of Link State Advertisements (LSAs) includes selectively blocking the broadcast or flooding of LSAs from spoke routers to other respective spoke routers in the hub and spoke area unless route leaking is permitted for a particular spoke router, or the particular spoke router has a backdoor connection, in which case, a full shortest path first (SPF) run may be scheduled for the particular spoke router such that the amount of protocol traffic may be minimized and the SPF runs in the hub and spoke area may be reduced.

Abstract: A server for authenticating subscribers in a tracking and locating system and method is disclosed. The locating system provides positional information of locator devices in the form of pages viewable by subscribers over a network.

Abstract: Methods and apparatus for achieving universal cross connect for Time Domain Modulated (TDM) data between a first and second data streams each having a corresponding time slot assignment are disclosed. Cross connect may be achieved through the use of a time slot assignment table.

Abstract: A method for performing an availability measurement on a networked system comprising: identifying at least one measurement point in the system; defining a measurement model configured to return a pass or fail result corresponding to a threshold sensed at the at least one measurement point and to a measurement function; measuring the system using the measurement model, wherein measuring the system comprises a plurality of measurements; collecting a plurality of pass or fail results from the plurality of measurements, wherein each one of the plurality of pass or fail results corresponds to a measurement point and to a measurement function of one or more measurements; and aggregating the plurality of pass or fail results to formulate a single availability value representing the availability of the system.

Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.

Abstract: A method for generating a substantially sinusoidal waveform containing encoded digital data having one of a first value and a second value at selected phase angles ?n comprises generating the waveform having an amplitude Y defined by a first function at phase angles lying outside of regions having a range ?? beginning at each phase angle ?n, said first function being Y=sin ?; generating the waveform having an amplitude Y defined by the first function at phase angles lying inside the regions having a range of ?? beginning at each phase angle ?n where data of the first value is to be encoded; and generating the waveform having an amplitude Y defined by a second function at phase angles lying inside the regions having a range of ?? associated with each phase angle ?n where data of the second value is to be encoded, the second function being different from Y=sin ?.