Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

Abstract: The present invention relates to stable, palatable, freeze-dried, fruit-based compositions. Specifically, the inventions relates to compositions of Açai fruit and Jucara fruit with high antioxidant capability and cyclooxygenase-inhibitory activity, and their uses. The invention further provides for methods of making stable, palatable, freeze-dried, fruit-based compositions from Açai fruit and Jucara fruit.

Abstract: An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.

Abstract: Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Abstract: An interactive, computer-implemented system for providing a comparison of at least two real estate properties is provided. The system includes a database that stores a plurality of data relating to real estate properties. The data includes at least one of address data, ownership data, size data, geographic location data and monetary value data. An interface system enables a system user to input a request for a comparison of at least a portion of the data for at least two of the real estate properties. The request includes information sufficient to identify the real estate properties to be compared. A processor uses the information to obtain a comparison of the data relating to the real estate properties. A delivery system provides to the system user a comparison of the data relating to the real estate properties.

Abstract: A process is disclosed for simultaneously extracting, saponifying, and isolating lutein without the use of harmful organic solvents. In one embodiment the method includes (a) dispersing Marigold oleoresin in an alkane hydrocarbon alkanol solution, (b) adding a potassium hydroxide to the Marigold oleoresin and alkane hydrocarbon alkanol solution to form a homogenous solution of Marigold oleoresin, (c) refluxing the homogeneous solution until ester hydrolysis of the Marigold oleoresin is completed, (d) cooling the homogeneous solution and allowing it to settle until lutein crystals are formed, and (e) washing the lutein crystals with methanol-hexane solution to separate and filter them from the solvents.

Abstract: A conference organizer uses conference software to define a conference and to store conference information on the organizer's computer system. The stored conference information includes a list of attendees, and a personal proxy mailbox for each attendee. Each attendee has a wireless device, such as a personal digital assistant (PDA). The organizer's computer system includes a wireless communication station that can communicate in wireless fashion with the wireless devices of the attendees at the conference. During the conference, an attendee uses his/her wireless device to access the conference information, select another attendee from the list of attendees, and send the selected attendee a message such that the message is stored in the personal proxy mailbox of the selected attendee. The use of personal proxy mailboxes allows attendees to send messages to one another and to receive messages from one another without divulging their primary email addresses.

Abstract: An interactive, computer-implemented system for providing a comparison of at least two real estate properties is provided. The system includes a database that stores a plurality of data relating to real estate properties. The data includes at least one of address data, ownership data, size data, geographic location data and monetary value data. An interface system enables a system user to input a request for a comparison of at least a portion of the data for at least two of the real estate properties. The request includes information sufficient to identify the real estate properties to be compared. A processor uses the information to obtain a comparison of the data relating to the real estate properties. A delivery system provides to the system user a comparison of the data relating to the real estate properties.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write strobe to compensate for timing drift at the memory device. The memory controller uses the read strobe as a measure of the drift.

Abstract: Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

Abstract: A Network Interface device (NI device) coupled to a host computer receives a multi-packet message from a network (for example, the Internet) and DMAs the data portions of the various packets directly into a destination in application memory on the host computer. The address of the destination is determined by supplying a first part of the first packet to an application program such that the application program returns the address of the destination. The address is supplied by the host computer to the NI device so that the NI device can DMA the data portions of the various packets directly into the destination. In some embodiments the NI device is an expansion card added to the host computer, whereas in other embodiments the NI device is a part of the host computer.