Abstract: An amorphous material containing silicon, carbon, hydrogen and nitrogen, provides a barrier/etch stop layer for use with low dielectric constant insulating layers and copper interconnects. The amorphous material is prepared by plasma assisted chemical vapor deposition (CVD) of alklysilanes together with nitrogen and ammonia. Material that at the same time has a dielectric constant less than 4.5, an electrical breakdown field about 5 MV/cm, and a leakage current less than or on the order of 1 nA/cm2 at a field strength of 1 Mv/cm has been obtained. The amorphous material meets the requirements for use as a barrier/etch stop layer in a standard damascene fabrication process.

Abstract: A charge pump system, including a charge pump and associated distributed clock generation circuitry, is provided for generating high voltages from a low initial voltage in applications such as erasing and programming electrically erasable programmable read only memory (EEPROM) arrays. The charge pump system uses a power supply voltage and a clock and includes a first phase bootstrapping circuit, an inverter, and a second phase bootstrapping circuit, and a two-stage charge pump. The two phase bootstrapping circuits are both responsive to the clock and use a distributed bootstrapping scheme to provide first and second phase clock signals with fixed multiples of the power supply voltage in order to overcome increased effective transistor threshold voltages, increase efficiency, and allow for charge boosting in a limited number of stages. The inverter is connected to the second phase bootstrapping circuit, causing the second phase clock signal to be opposite in phase from the first clock signal.

Abstract: A charge pump system includes a charge pumping circuit for outputting a high voltage VPP at a node. An oscillator circuit, coupled to the charge pumping circuit, drives the charge pumping circuit with at least one clock signal. A current source generates a pulldown current. A voltage divider circuit is coupled between the node and the current source. The voltage divider circuit cooperates with the current source to form a feedback loop for controlling the oscillator circuit to run at variable, optimum frequency for controlling the rate-of-rise and the amplitude of the high voltage VPP while minimizing power-supply current drain.

Abstract: A charge pump system and associated variable-amplitude clock generation circuitry are provided for generating high voltages from a low initial voltage in applications such as erasing and programming electrically erasable programmable read only memory (EEPROM) arrays. The charge pump system uses a power supply voltage and a clock and includes a first phase bootstrapping circuit, an inverter, and a second phase bootstrapping circuit, and charge pump circuitry. The two phase bootstrapping circuits are both responsive to the clock and provide first and second phase clock signals. The inverter is connected to the second phase bootstrapping circuit, causing the second phase clock signal to be opposite in phase from the first clock signal. The charge pump circuitry is responsive to the power supply voltage and the first and second phase clocks and uses native transistors that have lower threshold voltages.

Abstract: A high voltage generating circuit comprises a secondary high voltage detector, a secondary high voltage generator, a primary high voltage detector, and a primary high voltage generator. An active signal enables the secondary high voltage detector, which when active, asserts a second signal upon detecting a drop of a high voltage signal and/or in response to a first signal. The secondary high voltage generator boosts the high voltage signal in response to the second signal. The primary high voltage detector asserts the first signal upon detecting the drop in the high voltage signal. The primary high voltage generator boosts the high voltage signal in response to the first signal. Accordingly, in active mode, the secondary high voltage generator can quickly and accurately compensate for a drop in the high voltage signal, since the secondary high voltage detector signals the drop of the high voltage signal before a word line is enabled.

Abstract: A high power cold cathode gas discharge system employs two electrode structures, where each structure includes a plurality of sub-electrodes connected in parallel to a driver so that the current delivered by the system is spread over multiple sub-electrodes. Each sub-electrode is connected to the driver through a current limiting device such as a capacitor which limits the current delivered by each sub-electrode to be below a certain threshold. By spreading the current delivered by the system over multiple sub-electrodes, the useful life of the system will not be reduced because of sputtering, which results in a high power and long life fluorescent lamp and other gas discharge devices.

Abstract: A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is assigned an array address by an array mount. An memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array mount configuration is used to unconditionally select the device mounted.

Abstract: An optical transmission system that includes an optical amplifier coupled to the input of an optical modulator having at least two complementary output ports for providing complementary modulated optical output signals can be used such that the relative intensity noise (RIN) associated with the optical amplifier is coupled into the modulated optical output signals as common mode noise and can therefore be eliminated using a differential detection scheme. Removing the RIN associated with the optical amplifier advantageously increases the carrier to noise ratio (CNR) for the optical transmission system.

Abstract: A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.

Abstract: A method of forming a light-transmissive contact on a p-type Gallium nitride (GaN) layer of an optoelectronic device includes in one embodiment, introducing a selected metal in an oxidized condition, rather than oxidizing the metal only after it has been deposited on the surface of the p-type GaN layer. In some applications, the oxidized metal provides sufficient lateral conductivity to eliminate the conventional requirement of a second highly conductive contact metal, such as gold. If the second contact metal is desired, an anneal in an oxygen-free environment is performed after deposition of the second layer. The anneal causes the second metal to penetrate the oxidized metal and to fuse to the surface of the p-type GaN layer. In a second embodiment, the oxidation occurs only after at least one of the two metals is deposited on the surface of the p-type GaN layer.

Abstract: An implantable drug delivery pump includes a reservoir, a dispensing chamber adjacent to the reservoir, a dispensing passage provided along an interior surface of the dispensing chamber, and an actuator for applying a moving compressive force onto the dispensing passage. The pump is subcutaneously implantable in a patient, and a drug is injected into the reservoir through a septum provided on a housing for the reservoir. As the compressive force applied by the actuator moves along the dispensing passage, the drug preparation is simultaneously pushed out of the dispensing passage into a catheter for delivery to the desired site, and additional drug preparation is drawn into the dispensing passage from the reservoir. The actuator includes a rotating arm driven by an motor at a controllable rate.

Abstract: A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Abstract: A current source for providing matched currents at low and variable bias voltages. The current source includes a first circuit, a second circuit, and a biasing circuit. The first circuit provides a first current. The first circuit includes a first transistor with a control terminal, a first terminal, and second terminal. A second circuit provides an output current to an output node. The second circuit includes a second transistor with a control terminal, a first terminal, and second terminal. The biasing circuit includes a third transistor with a control terminal, a first terminal, and second terminal. The biasing circuit also includes a fourth transistor with a control terminal, a first terminal, and second terminal. The biasing circuit provides a voltage at the first terminal of the third transistor and a voltage at the control terminal of the second transistor so that a voltage at the first terminal of the second transistor and a voltage at the second terminal of the first transistor match.

Abstract: The performance of a computer architecture having cache memory is optimized by reorganizing the structure of information before such information is written into an external memory coupled to a processor. Specifically, loops of repeated processing steps are identified, each loop routine operating upon particular data and in response to particular instructions. The instructions and data for these loop routines are organized into structures of information, each of which comprises all instructions or data for one loop routine. Each structure is stored into external memory and can be brought into cache memory as a single block of information.

Abstract: A programmable integrated circuit device includes a plurality of output terminals, each output terminal for use in transmitting a respective output signal. Timing control circuitry is connected to the output terminals. The timing control circuitry is operable to delay the output signal on each output terminal and is further operable to control a slew rate of the output signal on each output terminal.

Abstract: The invention provides a method and system for combined unicast and multicast scheduling. Data cells are assigned at each input, to one unicast input queue for each output, or to a single multicast input queue. Each input makes two requests for scheduling to each output for which it has a queued data cell, one unicast request and one multicast request. Each output grants up to one request, choosing highest priority requests first, giving precedence to one such highest priority request using an output precedence pointer, either an individual output precedence pointer which is specific to that output for unicast data cells, or a group output precedence pointer which is generic to all outputs for multicast data cells. Each input accepts up to one grant for unicast data cells, or as many grants as possible for multicast data cells, choosing highest priority grants first, giving precedence to one such highest priority grant using an input precedence pointer.

Abstract: A fabricating method for a one-piece refractory metal rocket engine chamber is described. Hollow liner sections of a platinum group metal or alloy are inserted into a chamber barrel portion to form the combustion chamber, connecting into a conical portion, a venturi throat and into a second conical portion, forming an expansion nozzle exit of the chamber. The hollow liner sections correspond to the interior shapes of the chamber portions. A refractory metal split hollow mandrel completes an assembly which is subjected to a hot isostatic pressing cycle. This HIP cycle expands the hollow mandrel, supporting the liner, outward against the chamber wall, pressure bonding the liner sections to the chamber portions. Scarfed edges of the liner sections are also bonded. The split mandrel is then chemically removed from the chamber resulting in a lined rocket engine chamber.

Abstract: A vertical trench-gated power MOSFET includes MOSFET cells in the shape of longitudinal stripes. The body diffusion of each cell contains a relatively heavily-doped region which extends parallel to the length of the cell and contacts an overlying metal source/body contact layer at specific locations. In one embodiment, the contact is made at an end of the cell. In another embodiment, the contact is made at intervals along the length of the cell. In addition, the power MOSFET contains diode cells placed at intervals in the array of cells. The diode cells contain diodes connected in parallel with the MOSFET cells and protect the gate oxide layer lining the trenches from damage due to large electric fields and hot carrier injection. By restricting the areas where the body contact is made and using the diode cells, the width of the MOSFET cells can be reduced substantially, thereby reducing the on-resistance of the power MOSFET.

Abstract: The invention discloses a method of making solder ball mounting pads on a substrate that have better ball shear performance, ball thermal cycle reliability, ball attach yield, and ball positional tolerances, than the solder ball mounting pads of the prior art. The method includes providing a sheet of material having a layer of metal thereon, and patterning the layer to define a solder ball mounting pad therein. The pad includes a central pad having at least two spokes radiating outward from it. An insulative mask is formed over the metal layer, and an opening is formed in the mask such that the central pad and an inner portion of each of the spokes is exposed therethrough, and an outer portion of each of the spokes is covered by the mask. In one embodiment, the central pad, spokes, and opening in the mask are shaped and arranged with respect to each other such that the pad and exposed portion of the spokes form a radially symmetrical pattern within the opening.