Abstract: Systems and methods for processing data signals are described. In one implementation, a demodulator and a first decoder unit, such as a convolutional encoder or a quadrature amplitude modulation decoder, for receiving the output of the demodulator, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal are provided. The decoded signal may be passed through a de-interleaving unit to form a de-interleaved signal. The first location signal may be passed to an identifier unit which receives it, and from it produces a second error indication signal indicative of the errors in the de-interleaved signal. The de-interleaved signal and the second error indication signal may be transmitted to a redundancy decoder, where the signals may be used to perform redundancy decoding.

Abstract: A voltage supply arrangement is proposed, which provides a voltage from a first power range in a first operating mode and from a second power range in a second operating mode, to a first electrical load. The voltage supply arrangement includes a voltage converter which is coupled on the input side to a voltage input of the voltage supply arrangement and on the output side to a first connection of a first switch, which is connected at a second connection to a voltage output of the voltage supply arrangement for connection of a first electrical load. The voltage supply arrangement further includes a second switch, which is coupled at a first connection to the voltage input and at a second connection to the voltage output, and a drive circuit, which is configured to set the first and the second switch to the first or the second operating mode in response to a control signal.

Abstract: One embodiment of the invention provides a circuit. The circuit includes a switching unit configured to connect or disconnect a voltage domain to a supply voltage input. The switching unit includes a first switch, a second switch and a third switch. The circuit includes a control signal input configured to receive a switch control signal. The circuit includes a signal distribution unit that is configured to output the switch control signal to the first switch delayed by a first time interval and to output the switch control signal to the second switch and to the third switch delayed by a second time interval.

Abstract: Implementations and embodiments of decoders, encoder/decoder systems and converters are depicted and described.

Abstract: An integrated semiconductor component includes a functional circuit and a power control circuit configured to generate a supply voltage from an input voltage. The power control circuit may include a snitching controller and a control circuit configured to set a frequency spectrum of tile Supply voltage and coupled to the switching controller. The control circuit may be configured to determine a current operating state out of at least two possible operating states of the integrated semiconductor component and to set the frequency spectrum dependent from the current operating state.

Abstract: A system for processing a data signal (such as an ADSL or VDSL signal) includes a first decoder unit, such as a convolutional decoder or a QAM decoder, for receiving the data signal, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal. A redundancy decoder employs the decoded signal and the first error indication signal (or transformed versions thereof) to perform redundancy decoding.

Abstract: Embodiments related to arbitration are described and depicted.

Abstract: A fuse link of undoped material is connected between first and second doped material contact regions and a layer of conductive material is located above the first and second contact regions and the fuse link. According to other embodiments, a fuse link is connected between first and second contact regions. A layer of conductive material is above the first and second contact regions and the fuse link, and a heat sink is in proximity to the fuse link. In a method, a programming pulse is applied to a fuse link of undoped material connected between first and second doped material contact regions to generate electromigration drift of a conductive material above the first and second contact regions and the fuse link.

Abstract: Embodiments of a digital-to-analog converter (DAC) with a logarithmic response and methods for converting digital signals to analog are generally described herein. Other embodiments may be described and claimed. In some embodiments, the DAC includes a wedge-shaped resistive array having a plurality of linearly-spaced contact nodes and a switching array to selectively couple one of the contact nodes with an analog output based on a control signal. Each of the contact nodes may provide a corresponding reference voltage that varies logarithmically with respect to the linearly-spaced contact nodes.

Abstract: The present invention relates to a device and a method for regulating the output power of an amplifier stage, e.g. an amplifier stage in a mobile data transmission system.

Abstract: An apparatus described herein is an LC tank circuit that may include a capacitance, a first inductance, and a second inductance. The first inductance and the second inductance may each be center tapped coils.

Abstract: Disclosed are techniques for generating a precisely controlled analog signal. In one described implementation, a semiconductor circuit is mounted on a circuit board having a power and a ground etching. The circuit has a power terminal coupled with the power etching and a ground terminal coupled with the ground etching. The circuit includes a trapezoid shaped resistive strip coupled with the power terminal and the ground terminal. Contacts are connected along one edge of the strip to provide outputs at various voltage levels. Switches having a common output are coupled with the contacts on the strip. A control circuit activates the switches so that the common output generates an analog signal.

Abstract: A transmitter includes an output. A coupler receives at least a derivative of the output and provides a feedback signal. A demodulator receives the feedback signal and performs an additive mixing to demodulate the feedback signal.

Abstract: Implementations are presented herein that relate to a memory cell, a memory device, a device and a method of accessing a memory cell.

Abstract: A transmitting arrangement includes a matching circuit, a reference circuit and a comparator. The output of the matching circuit can be coupled to an antenna and comprises an adjustable impedance. The reference circuit is connected to an input of the matching circuit and comprises a reference impedance. Inputs of the comparator are coupled to the matching circuit and the reference circuit and its output is coupled to the adjustable impedance via a control input of the matching circuit.

Abstract: In some embodiments, a circuit includes a power amplifier including an input terminal configured to receive an input signal and an output terminal to provide an RF voltage, the output terminal coupled to a load, a current sensor configured to sense the current drawn by the power amplifier and provide a first sensor output signal dependent upon current consumption when the current exceeds a predetermined current threshold, a voltage sensor configured to sense the output power of the power amplifier and provide a second sensor output signal when the RF voltage during up ramp falls below a predetermined threshold voltage, and a summing circuit configured to receive the first and second sensor output signals and provide a feedback signal including a combination of a power dependent contribution and either of a voltage dependent contribution or a current dependent contribution.

Abstract: A method in the fabrication of an integrated circuit including a PMOS varactor and an npn transistor, comprises the steps of (i) simultaneously forming buried n+-doped regions (31) for the PMOS varactor and the npn transistor in a p-doped substrate (10, 41); (ii) simultaneously forming n-doped wells (41) above the buried n+-doped regions (31); (iii) simultaneously forming field isolation areas (81) around the n-doped regions (41); (iv) forming a PMOS gate region (111, 194) and a p-doped base each in a respective one of the n-doped wells (41); and (v) simultaneously forming n+-doped contacts to the buried n+-doped regions (31); the contacts being separated from the n-doped wells (41). Source and drain regions may be formed in the PMOS n-well (inversion mode) or the PMOS n+-doped contact may be formed in the PMOS n-well instead of being separated from there (accumulation mode).

Abstract: This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.

Abstract: Embodiments of the invention relate generally to an apparatus, to an embedded memory, to an address decoder, to a method of reading out data and to a method of configuring a memory. In an embodiment of the invention an apparatus is provided. The apparatus may include a plurality of read-only memory (ROM) cells and an address decoder to access a ROM cell of the plurality of ROM cells, the address decoder further being fuse-programmable to divert an access to the ROM cell to a different memory cell.

Abstract: A switching control circuit for a DC-DC converter comprises an input terminal to receive input signals and an output terminal to couple the switching control circuit to a switch of the DC-DC converter. A quasi-static supply path is coupled to the input terminal to receive first signals based on the input signals and coupled to the output terminal to provide output signals to the output terminal based on the input signals. A dynamic supply path is coupled to the input terminal to receive second signals based on the input signals in-phase with the first signals and coupled to the output terminal to provide output signals to the output terminal based on the input signals.