Patents Represented by Attorney, Agent or Law Firm Stanton C. Braden
  • Patent number: 8311120
    Abstract: This disclosure describes techniques for coding mode selection. In particular, an encoding device determines whether or not to code a block of pixels in a coding mode currently being considered for selection using information associated with at least one other coding mode with a different block partition. In one aspect, the encoding device uses information associated with at lest one coding mode that has block partitions that are sub-partitions of the block partitions of the coding mode currently being considered for selection. Additionally, the encoding device may use information associated with another coding mode that has the same block partitions as the coding mode currently being considered for selection or information associated with the coding mode currently being considered for selection.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: November 13, 2012
    Assignee: Qualcomm Incorporated
    Inventor: Vinod Kaushik
  • Patent number: 8239766
    Abstract: This disclosure is directed to techniques for encoding and decoding transitional effects, i.e., visual video effects that are used to transition from a current scene of a multimedia sequence. According to the disclosed techniques, an encoding device detects a transitional effect associated with a multimedia sequence during the encoding of the multimedia sequence, and transmits information as part of an encoded multimedia sequence to identify the transitional effect associated with the encoded multimedia sequence to a decoder. The information may comprise metadata that can be used by the decoder to simulate or re-create the transitional effect. The decoder simulates a transitional effect in response to the information.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: August 7, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Tao Tian, Fang Shi, Vijayalakshmi R. Raveendran
  • Patent number: 8064880
    Abstract: A general global gateway (GGG) uses shared secret data to authenticate between a CDMA network and a GSM network such that a mobile station having a subscription in a GSM network can roam into a CDMA network and be authenticated to use the CDMA network without having a complete ANSI-41 subscription. The goal of authenticating a GSM subscriber in an ANSI-41 network using GSM authentication credentials is achieved by substituting encryption key Kc as SSD-A in the standard ANSI-41 computation of AUTHR using a CAVE algorithm.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: November 22, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Nikhil Jain, Bruce Collins
  • Patent number: 8009551
    Abstract: The subject invention selects a starting sub-carrier frequency group for a pilot staggering sequence to facilitate in mitigating the possibility of pilot signal collisions. In one embodiment, a randomized starting sub-carrier frequency group of the pilot is utilized in a first orthogonal frequency division multiplexing (OFDM) symbol of a frame. In another embodiment, a starting pilot sub-carrier frequency group number is determined by utilizing a random number generator such as, for example, a Pseudo-Noise (PN) sequence generator, seeded by a network identification (ID) number. In this manner, the starting sub-carrier frequency group is specific to that particular network. The subject invention also provides a more scalable system through the trading of system bandwidth for coverage.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: August 30, 2011
    Assignee: QUALCOMM Incorporated
    Inventor: Michael Mao Wang
  • Patent number: 7995460
    Abstract: A control interface protocol governs communications in a satellite telephone system. The satellite telephone system comprises a radio antenna unit (RAU) and a plurality of desksets connected to the RAU. An interface bus connects the desksets to the RAU. The RAU and the desksets communicate with each other by packets. Each packet comprises a start of header (SOH) byte, an address number (ADDR) byte, a command (CMD) byte, an argument (ARG) and a block check character (BCC). The ADDR byte comprises a source and a destination address of the packet. All packets, except negative acknowledgment (NAK) packets from the desksets, are acknowledged by the RAU. The packets originating from the desksets are tagged with an address of the desksets. A packet to a specific deskset includes a destination address. A packet originating from the RAU to all desksets includes a first default address. A packet originating from the RAU to a deskset that does not have an address includes a second default address.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: August 9, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Clement B. Edgar, III, R. Nicholson Gibson
  • Patent number: 7839831
    Abstract: Methods and apparatus for time tracking using assistance from TDM pilots in a communication network. In an aspect, a method is provided for time tracking in a device operating on a communication network, wherein the device performs a time tracking algorithm. The method includes determining a delay spread, and modifying at least one parameter used by the time tracking algorithm based on the delay spread. In another aspect, an apparatus is provided for time tracking in a device operating on a communication network, wherein the device performs a time tracking algorithm. The apparatus includes computation logic for determining a delay spread, and control logic for modifying at least one parameter used by the time tracking algorithm based on the delay spread.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: November 23, 2010
    Assignee: QUALCOMM Incorporated
    Inventors: Bojan Vrcelj, Ashok Mantravadi, Krishna Kiran Mukkavilli, Raghuraman Krishnamoorthi
  • Patent number: 6346821
    Abstract: A method is provided for nondestructive measurement of minority carrier diffusion (Lp) length and accordingly minority carrier lifetime (Óp) in a semiconductor device. The method includes the steps of: reverse biasing a semiconductor device under test, scanning a focused beam of radiant energy along a length of the semiconductor device, detecting current induced in the DUT by the beam as it passes point-by-point along a length of the DUT, detecting current induced in the semiconductor device by the beam as it passes point-by-point along the scanned length of the semiconductor device to generate a signal waveform (Isignal), and determining from the Isignal waveform minority carrier diffusion length (Lp) and/or minority carrier lifetime (Óp) in the semiconductor device.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: February 12, 2002
    Assignee: Infineon Technologies AG
    Inventor: Helmut Baumgart
  • Patent number: 6331459
    Abstract: A method of forming a dynamic random access memory cell in a semiconductor substrate. The cell has a transistor in an active area of the semiconductor substrate electrically coupled to a storage capacitor through a buried strap or coupling region. The method includes forming an electrode for the capacitor in a lower portion of a trench in the semiconductor substrate. A sacrificial material is formed on the sidewall portion of the trench, such sacrificial material extending from the surface of the semiconductor substrate into the substrate beneath the surface of the semiconductor substrate. The active area for the transistor is delineated and includes forming a covering material over the surface of the semiconductor substrate with a portion of the sacrificial material being projecting through the covering material to expose such portion of the sacrificial material.
    Type: Grant
    Filed: February 18, 1999
    Date of Patent: December 18, 2001
    Assignee: Infineon Technologies AG
    Inventor: Ulrike Gruening
  • Patent number: 6329271
    Abstract: A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.
    Type: Grant
    Filed: June 6, 2000
    Date of Patent: December 11, 2001
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Hiroyuki Akatsu, Yujun Li, Jochen Beintner
  • Patent number: 6327170
    Abstract: An integrated circuit comprising first and second bitline pairs 410 and 420 is described. The bitline paths of a bitline pair are on different bitline levels. The bitline paths of the first and second bitline pairs which are on different bitline levels are adjacent to each other. The first bitline pair comprises m vertical-horizontal twists 440, where m is a whole number≧1, and the second bitline pair comprises n vertical-horizontal twists 460 and 461, where n is a whole number≠m. The vertical-horizontal twists transform coupling noise into common mode noise.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: December 4, 2001
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Mueller, Ulrike Gruening
  • Patent number: 6323535
    Abstract: A fuse for semiconductor devices, in accordance with the present invention, includes a cathode including a first dopant type, and an anode including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link connects the cathode and the anode and includes the second dopant type. The fuse link and the cathode form a junction therebetween, and the junction is configured to be reverse biased relative to a cathode potential and an anode potential. A conductive layer is formed across the junction such that current flowing at the junction is diverted into the conductive layer to enhance material migration to program the fuse.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: November 27, 2001
    Assignees: Infineon Technologies North America Corp., International Business Machines Corporation
    Inventors: Sundar K. Iyer, Peter Smeys, Chandrasekhar Narayan, Subramanian Iyer, Axel Brintzinger
  • Patent number: 6324125
    Abstract: A semiconductor circuit is provided including circuitry for producing a pulse. A plurality, n, of delay elements are provided each enabled and disabled in parallel by the pulse. Each delay element is adapted to transmit the pulse from an input to an output, with the pulse reaching the respective outputs at different times. A plurality, n−1, of detectors is provided each having an input coupled to an input of a corresponding delay element. Each detector is adapted to set a state of its output to a predetermined state, from a plurality of states, in response to receiving a portion of the pulse. The outputs of the detectors are coupled to output pins of the semiconductor circuit. A tester is provided that is adapted to couple to the semiconductor output pins and detect the state of the detector outputs.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: November 27, 2001
    Assignee: Infineon Technologies AG
    Inventors: Gerd Frankowsky, Hartmud Terletzki
  • Patent number: 6320803
    Abstract: There is provided method and apparatus for improving and making more effective the testing of very large scale integrated (VLSI) devices such as a synchronous random access memory (SDRAM), along with improving their performance and their yield in production. The method includes the steps of providing a VLSI device with switching circuitry which permits respective arrays or banks of the device to be tested alone or simultaneously with separate sequences of test mode signals to identify defects, interactions and unwanted limitations in the overall performance of the device; using the information thus obtained to modify the test mode signals and where indicated the design of the device; iterating the previous steps to optimize a test methodology for the device; and using the optimized test methodology during burn-in of production devices. Logic circuitry is added to a VLSI device to facilitate the improved testing capability.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: November 20, 2001
    Assignees: Infineon Technologies AC, Kabushiki Kaisha Toshiba, International Business Machines Corporation
    Inventors: Martin Gall, Wayne Ellis, Shinji Miyamoto, Masahiro Yoshihara
  • Patent number: 6319788
    Abstract: A method for fabricating a trench capacitor wherein the trench in the substrate. The walls of the trench are lined with a semiconductor material having a substantially uniform thickness over sidewalls of the trench, such trench being void of the material in an inner region of the trench. A dielectric collar is formed in an upper portion of the trench above the semiconductor material. The semiconductor material is removed from the bottom portion of the trench. A node dielectric is formed that lines the collar and trench sidewalls at the bottom portion of the trench. The trench is filed with a doped semiconductor material, such doped semiconductor material providing an electrode of the trench capacitor. The trench is forming includes forming the trench with a diameter of the lower portion of the trench effectively at least equal to about the upper portion of the trench.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: November 20, 2001
    Assignees: Infineon Technologies North America Corp., International Business Machines Corporation
    Inventors: Ulrike Gruening, Martin Schrems, Carl J. Radens
  • Patent number: 6319787
    Abstract: A trench capacitor having a substrate with a trench extending therein with a nested, e.g., concentric, conductive regions disposed within the trench. A dielectric material is disposed within the substrate. The dielectric material has portions thereof disposed between the concentric conductive regions to dielectrically electrically separate one of the conductive regions from another one of the conductive regions. The dielectrically separated conductive regions provide a pair of electrodes for the capacitor. Selected ones of the concentric conductive regions are electrically connected to provide one of the electrodes for the capacitor. The substrate has a conductive region therein and one of the concentric conductive regions providing one of the electrodes is electrically connected to the conductive region in the substrate. One of the concentric conductive regions is electrically connected to a conductive region in the substrate through a bottom portion of the trench.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: November 20, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventors: Gerhard Enders, Matthias Ilg, Dietrich Widmann
  • Patent number: 6313663
    Abstract: A bidirectional full swing voltage repeater implemented on a signal line of an integrated circuit, which includes a first enable node for providing a first enable signal and a second enable node for providing a second enable signal. There is included a first full-swing unidirectional repeater circuit coupled between a first portion of the signal line and a second portion of the signal line. The first full-swing unidirectional repeater is configured to pass a first full swing signal from the first portion of the signal line to the second portion of the signal line when the first enable signal is enabled. The second full-swing unidirectional repeater circuit is coupled between the first portion of the signal line and the second portion of the signal line.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: November 6, 2001
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Gerhard Mueller, David R. Hanson
  • Patent number: 6310511
    Abstract: Apparatus is used to dynamically control the power output of generators of a generator system on a chip to load circuits on the chip. A power bus is directed along at least one “spine” section on the chip which may intersect with at least one “arm” section on the chip for supplying power from the generators, which are coupled to the power bus in the “spine” section thereof, to circuits on the chip. The power bus has a feedback lead from each end which is remote from the generators for providing a continuous measurement of a voltage drop occurring at each remote end. At least one detector circuit is located at a predetermined point adjacent the generators of the chip for comparing a voltage from the generators measured at the predetermined point with the concurrent voltage drop measured at an associated remote end.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: October 30, 2001
    Assignee: Infineon Technologies AG
    Inventor: Oliver Weinfurtner
  • Patent number: 6310375
    Abstract: The present invention provides a trench capacitor, particularly for use in a semiconductor memory cell (100), having an isolation collar (168) with a trench (108) formed in a substrate (101); said isolation collar (168) formed in the upper region of said trench (108); an optional buried plate (165) in said substrate region surrounding said lower region of said trench (180) as a first capacitor plate; a dielectric layer (164) for lining said lower region of said trench (108) and said isolation collar (168) as capacitor dielectric; and a conductive second fill material (161) filled in said trench (108) as a second capacitor plate; wherein said diameter of said lower region of said trench (108) is at least equal to said diameter of said upper region of said trench (108). Moreover, the invention provides a corresponding manufacturing method.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: October 30, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventor: Martin Schrems
  • Patent number: 6307781
    Abstract: A two transistor cell NOR architecture flash memory is provided wherein the floating gate transistor is couple between the selection transistor and an associated bit line. The flash memory is deposited within a triple well and operates according to a Fowler-Nordheim tunnel mechanism. Programming of memory cells involves tunneling of carriers through gate oxide from a channel region to a floating gate rather than tunneling from a drain or source region to the floating gate.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: October 23, 2001
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventor: Danny Pak-Chum Shum
  • Patent number: 6307397
    Abstract: A method in an integrated circuit for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals. The reduced voltage signals has a voltage level that is below VDD. The reduced voltage repeater circuit is configured to be coupled to the signal line and having an input node coupled to a first portion of the signal line for receiving a first reduced voltage signal and an output node coupled to a second portion of the signal line for outputting a second reduced voltage signal. The method includes coupling the input node to the first portion of the signal line. The input node is coupled to an input stage of the reduced voltage repeater circuit. The input stage is configured to receive the first reduced voltage signal on the signal line. The input stage is also coupled to a level shifter stage that is arranged to output a set of level shifter stage control signals responsive to the first reduced voltage signal.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: October 23, 2001
    Assignee: InfineonTechnologies AG
    Inventors: Gerhard Mueller, David R. Hanson