Abstract: A method is provided for detecting a discontinuity in electrical connections of a microchip that includes an input pin connected to a voltage supply line, multiple circuit sections, an output voltage line for connecting the circuit sections to an output pin, and a resistive output divider. According to the method, there is determined a number of electrical connections as a function of the short circuit current for the input and output pins. The voltage supply line is sectioned as a function of the number of electrical connections determined for the input pin, and the sections of the voltage supply line are connected independently to the circuit sections. The output voltage line is sectioned as a function of the number of electrical connections determined for the output pin. As a function of the number of electrical connections determined, the number and value of the resistances of the output divider is increased.

Abstract: An injection mold is provided for injection molding an encapsulation material to encapsulate at least one integrated circuit chip. The injection mold includes at least two parts that define at least one injection circuit, and at least one blind complementary channel communicating with the injection circuit. The injection circuit includes at least one injection cavity for housing the chip, at least one transfer chamber from which the encapsulation material is injected, and at least one injection channel connecting the transfer chamber to the injection cavity. The blind complementary channel is formed between the two parts of the mold and forms at least one appendage of encapsulation material that is connected to the encapsulation material that fills the injection circuit. Also provided is a method for injection molding an encapsulation material to encapsulate at least one integrated circuit chip.

Abstract: A method is provided for reserving a portion of web to be used as a leader portion. A measurement of the length of a web is obtained, and a plurality of print jobs are received. At least one print job length is determined, and an operation involving the at least one print job length and the web length is performed. In a preferred embodiment, the operation is performed by subtracting a sum of the lengths of the plurality of print jobs from the web length to obtain a difference. Also provided is a system for producing custom printed articles.

Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

Abstract: An element is deposited by flowing a gas through a solid donor compound that includes the element, and over a substrate. The flow of gas deposits a film of a few monolayers of donor compound on the substrate. An optical radiation source (e.g., a femtosecond laser) which produces optical radiation at an instantaneous intensity sufficient to cause non linear or otherwise enhanced interaction between optical radiation photons and the donor compound is used to decompose the donor compound and deposit the metal on the substrate. After an initial deposit of the donor compound is produced, optical radiation can be absorbed and heat the substrate in the localized area of the deposit in order to accelerate the deposition process by thermally decomposing the donor compound.

Abstract: A generator circuit for voltage ramps is provided that includes a differential stage with positive feedback coupled between a first and a second voltage reference and having a first output connected to a control terminal of a first output transistor. The first output transistor is connected at an output terminal of the ramp generator circuit to a capacitive charge to be biased with voltage ramps. The ramp generator circuit also includes a second output transistor parallel connected to the first output transistor and having the control terminal connected to a second output of the differential stage.

Abstract: A sense amplifier for a memory includes a comparator and a bit line polarization circuit. The comparator receives a first signal representative of a current flowing through a memory cell and a second signal representative of a reference current. Additionally, the comparator includes a stage in a common source configuration and an active load for the stage, and the bit line polarization circuit provides a polarization voltage level that is independent of the supply voltage level. In a preferred embodiment, the sense amplifier also includes an output stage that improves switching time at high supply voltages.

Abstract: A device for switching radio frequency signals that includes at least a first MOS transistor for selectively interrupting or transmitting the signals between at least first and second terminals as a function of a control signal. The gate of the first MOS transistor is connected to the first terminal, and both the drain and source of the first MOS transistor are connected to the second terminal. In a preferred embodiment, the first MOS transistor selectively interrupts or transmits the signals between the first terminal and the second terminal, and the device also includes a second MOS transistor for selectively interrupting or transmitting the signals between the first terminal and a third terminal. A system for processing radio frequency signals is also provided.

Abstract: A method for communicating between a transmitting unit and a receiving unit over a synchronous serial link. A messages formed by elementary messages is transmitted from the transmitting unit to the receiving unit, with each of the elementary messages including a useful information word. There is established a time gap composed of multiple elementary temporal units after each elementary message is transmitted by the transmitting unit, with the transmitting unit not transmitting during the time gap. During the time gap, an acknowledgement word is received from the receiving unit. The acknowledgement word includes at least one reception bit that is selectively positioned at one of the elementary temporal units of the time gap, and the transmitting unit determines the elementary message that is to be transmitted next based at least partially on at which elementary temporal unit of the time gap the received at least one reception bit is positioned.

Abstract: A method and a computing system compute an incremental checksum corresponding to a data packet. The incremental checksum is computed within one processor cycle of a processor. A first register (102) stores first checksum information corresponding to a data packet. A second register (104) stores second checksum information corresponding to old information being deleted from the data packet. A third register (106) stores third checksum information corresponding to new information being added to the data packet. An incremental checksum circuit (100), electrically connected to the first register (102), to the second register (104), and to the third register (106), provides resulting checksum information corresponding to the data packet after deleting the old information from the data packet and adding the new information to the data packet. The resulting checksum information is selectively stored in the first register (102).

Abstract: A circuit structure integrated in a semiconductor substrate comprises at least one pair of transistors each being formed each in a respective active area region and having a source region and a drain region, as well as a channel region intervening between the source and drain regions and being overlaid by a gate region. The gate regions are connected electrically together by an overlying conductive layer and respective contacts. The contacts between the gate regions and the conductive layer are formed above the active areas.

Abstract: A method for detecting the lock-in of a loop that synchronizes an internal clock on the transmission of value pairs provided by a demodulator. According to the method, a module of a vector that has as components the values of one of the value pairs is calculated, and the module is compared with a threshold that is smaller than a theoretical module. The locked-in condition is determined according to the ratio of the number of modules found to be greater than or smaller than the threshold to the total number of modules. In one preferred method, the threshold is incremented by a first value if the module is greater than the threshold and is decremented by a second value if the module is less than the threshold. A lock-in detection circuit for detecting the lock-in of a loop is also provided. A calculation circuit calculates a module of a vector that has as components the values of one of the value pairs. A register stores a threshold and a comparator compares the stored threshold with the calculated module.

Abstract: A current reference circuit for low supply voltages is provided. The current reference circuit includes a series including a resistor and a diode, a current source having one terminal coupled to a supply voltage and another terminal coupled to the series, an operational amplifier having its negative electrode connected to a band gap reference voltage, and a transistor. The diode has its cathode electrode coupled to ground and its anode electrode coupled to the resistor. The transistor has its gate electrode coupled to the output of the operational amplifier, its source electrode coupled to ground, and its drain electrode coupled to both the positive electrode of the operational amplifier and the current source. Also provided are an integrated circuit that includes at least one current reference circuit for low supply voltages and a signal processing system that includes at least one current reference circuit for low supply voltages.

Abstract: A method of controlling an electronic circuit is provided. A command is received from a control unit. The command is interpreted in either a first manner if the command is followed by a predetermined dead time, or a second manner if a new command is transmitted before expiration of the predetermined dead time. In a preferred embodiment, the command is interpreted in the second manner only if the new command is identical to the command. Also provided is a chip card that includes an antenna, at least one memory, and a control circuit. When a command is received, the control circuit performs either a first function if the command is followed by a predetermined dead time, or a second function if a new command is transmitted before expiration of the predetermined dead time. Additionally, a telephone apparatus is provided that includes a read/write device for contactless control of a chip card. The read/write device includes an antenna and a control circuit.

Abstract: A system includes an integrated circuit device that compares the relative phase of first and second signals to a very high precision. The system includes a first input for receiving the first signal with a first edge, and a second input for receiving the second signal with a second edge. A first delay chain includes a first at least one delay element, and the first signal is delayed across the first at least one delay element, each of the first at least one delay element includes an output tap. A second delay chain includes a second at least one delay element, the second signal is delayed across the second at least one delay element, each of the second at least one delay element includes an output tap.

Abstract: A method of determining the time for polishing the surface of an integrated circuit wafer on a polishing machine. A sample wafer is fabricated to include at least one high plateau and at least one low plateau joined by a sudden transition. At least one initial profile is topographically scanned, and the surface of the sample wafer is polished at a particular polishing pressure for a particular polishing time. The final profile of the polished layer is topographically scanned in the corresponding area, and the initial and final topographical scans of the sample wafer are converted into Fourier series. The surface of the wafer to be polished is topographically scanned, and the topographic scan of the wafer to be polished is converted into a Fourier series. The time for polishing the wafer to be polished is calculated from the Fourier series and the average thickness to be removed.

Abstract: A buffer for adapting data flows from input channels to output channels is provided. The buffer includes a DRAM organized in blocks and a memory controller for managing assignment of the blocks to the chains of linked blocks. The DRAM contains, as a chain of linked blocks, data associated with each communication channel formed by a pair of input and output channels, and also contains a main queue of free blocks for listing unoccupied blocks. The memory controller includes a cache memory containing a partial queue of free blocks that the memory controller uses in managing block assignment. According to one embodiment, when a level of the partial queue reaches a predetermined minimum limit the cache memory is at least partially filled by a burst from the main queue, and when a level of the partial queue reaches a predetermined maximum limit the cache memory is at least partially emptied by a burst into the main queue.

Abstract: A method for converting a rectilinear image and a focal length into a cylindrical image parameterized by a height of the cylinder and an angular distance in a single buffer on a remote processing device. The method, on the remote processing device, comprising joining two or more images together to form a panoramic image with corrected perspective. The rectilinear transformation is “in-place” and requires only one buffer. Color correction and motion estimation is also carried out on the remote device. In an alternate embodiment, a computer readable medium corresponding to the above method is described.

Abstract: A method is provided for performing multiplication with accumulation in a Galois Field on a first data, a second data, and a third data, with each of the data being coded on 2 n bits. A first multiplication, in the sense of the arithmetic of a Galois Field, is performed on the first data and the n lowest weight bits of the second data to produce a first intermediate result coded on 3 n bits, and a first addition, in the sense of the arithmetic of a Galois Field, is performed on the third data and the first intermediate result to produce a second intermediate result on 3 n bits.

Abstract: An audio signal is sampled and a frequency transform is performed on a succession of sets of samples of the signal to obtain a time dependent power spectrum for the audio signal. Frequency components output by the frequency transform are collected in frequency bands. More than one running average is taken of each semitone frequency band. When the values of two running averages of the same semitone frequency band cross, time information is recorded. Information about average crossing events that have occurred at different times in a set of adjacent semitone frequency bands is combined to form a key. A set of keys obtained from a song provides a means for identifying the song and is stored in a database for use in identifying songs.