Abstract: An analog-to-digital converter (ADC) (112) for sampling high speed video signals includes Pre-amplifiers (502, 504, 506) electrically coupled to Post-amplifiers (508, 510, 512) that are electrically coupled to output latches (514, 517, 519, 521, 523, 525, and 527). A sampling clock signal (116) clocks the output latches (514, 517, 519, 521, 523, 525, and 527) to sample an input analog electronic signal to provide a digital representation thereof. The ADC (112) includes an auto-zeroing function to cancel bias voltages at the Post-amplifiers (508, 510, 512) during a video signal horizontal blanking time period. The ADC (112) includes a bit dithering function by alternating sets of reference voltages into the Pre-amplifiers (502, 504, 506) increasing bit resolution. The ADC (112) includes wired interconnect interpolation between the Pre-amplifiers (502, 504, 506) and Post-amplifiers (508, 510, 512) and between the Post-amplifiers (508, 510, 512) and the output latches (514, 517, 519, 521, 523, 525, and 527).

Abstract: Disclosed is a bootstrap circuit in DC/DC static converters having the characteristic of comprising a fixed frequency signal, a recharge circuit of a capacitor and current generator means, said generator means controlled so as to emit current pulses, in synchrony with said fixed frequency signal, of a predetermined duration, every time that charge accumulated by said capacitor goes below a predetermined level.

Abstract: A method is provided for displaying an OSD on a video image. According to the method, values of pixels of the OSD are stored, and pixels of lines of the OSD that are to be displayed without processing are displayed by making direct use of a color look-up table. Additionally, pixels of lines of the OSD that are to be displayed after processing with a mathematical filter and/or that are required for computations associated with the mathematical filter are processed. In the processing step, the pixels of the lines to be processed are stored in the form of addresses that designate the memory lines of the color look-up table, the values of the pixels of the lines to be processed are obtained by an addressing of the color look-up table, and a mathematical filter is applied to the obtained values of the pixels to be processed.

Abstract: A frequency test circuit (200) includes a built-in self test (BIST) circuit (212) which provides for testing of a frequency generating circuit such as an oscillator circuit (100). The test circuit (200) includes circuit stages (202-208) which help produce a reference signal (210) which has substantially the same frequency as that produced by the oscillator circuit (100) when it is operational. Since the low current oscillator circuit (100) can fail at any one of the divider or level shifting stages (106-112), the test circuit (200) can determine if the reference signal and the output signal of the oscillator have substantially the same frequency and produce a test condition signal indicative of either a pass or failed test at test port (214).

Abstract: The present invention relates to messaging systems in general and message broker systems in specific. More particularly, the invention relates to means and a method for processing message publication requests and message subscription requests. The current invention transforms the subscription problem into a database query problem allowing to use query techniques known and optimized for many years. The basic approach of the current invention is to invert the relationship of message publication requests (treated as database data) and message subscription requests (treated as database queries) according the state of the art. Thus the core of the current invention is to treat incoming messages publication requests as database queries and to treat message subscription requests as database queries.

Abstract: An electroplating bath includes two electrolytes that are separated by a low ionic mobility barrier substance. Electroplating substrates can be transferred between the two electrolytes, through the barrier substance. Successive layers can be deposited by alternately electroplating in the two electrolytes. The substrate need not be brought through an air-liquid interface in transferring it between the two electrolytes. More than one anode can be provided in each electrolyte for depositing alloy film layers. A dummy electrode can be provided in each electrolyte to be used in lieu of the substrate in order to change concentrations of compounds in each electrolyte so that sharp compositional transitions between successive layers deposited on the substrate can be obtained.

Abstract: A driver circuit for driving a plasma display panel comprising a plurality of cells arranged in a matrix of lines and columns; comprising a set of driver output stages connected to line or column electrodes to which a first electrode of cells of a same line or a same column are connected, respectively. The driver circuit includes a detection device for detecting a short circuit between two or more of the outputs of the driver output stages. It allows to test for alignment faults in the flexible cable connecting together the driver module housing incorporating the driver circuit and the electrodes of the plasma display panel.

Abstract: A testing device for testing dynamic characteristics of an electronic circuit using serial transmissions. The circuit includes a multiplexing device and a demultiplexing device for implementing a serial link in the component or circuit. The testing device includes a transmitter for transmitting binary signals to the multiplexing device, a receiver for receiving binary signals from the demultiplexing device, and a link for selectively providing a coupling between the transmitter and the receiver. Additionally, a clock generator delivers a first clock signal to the transmitter and a second clock signal, which has a different frequency than the first clock signal, to the receiver. In one preferred embodiment, the clock generator includes a single programmable-frequency oscillator and a variable delay circuit. The programmable-frequency oscillator delivers the first clock signal and the variable delay circuit delays the first clock signal to deliver the second clock signal.

Abstract: A system includes a signal reconstruction controller (110) electrically coupled to at least one analog-to-digital converter (ADC) (112) and to a phase adjustable clock source (108). A sampling clock signal (116) is electrically coupled from the clock source (108) to the at least one ADC (112). The at least one ADC (112) samples an electronic signal according to the sampling clock signal (116) to provide a digital representation of the electronic signal. The controller (110) samples data from the ADC (112) at different sampling points in the electronic signal and determines the edges (140) of the electronic signal and the noisy samples (142, 144) that are away from the edges (140) of the electronic signal. By finding the least noisy sample (146, 148) that is away from the edges (140) of the electronic signal the controller (110) adjusts the phase of a sampling signal clock (116) to a sampling point that is the most reliable to sample the electronic signal to provide a digital representation thereof.

Abstract: A phase locked loop is provided that includes a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator. The charge pump circuit includes two symmetric branches, feedback paths, and circuit breaking switches. Each of the symmetric branches has a constant current generator and a pulsed current generator, with one terminal of the loop filter being connected to one of the symmetric branches and the other terminal of the loop filter being connected to the other of the symmetric branches. The feedback paths control the constant current generators based on voltages at the terminals of the loop filter, and each of the circuit breaking switches couple one of the pulsed current generators and the corresponding terminal of the loop filter. The pulsed current generators supply a first current whose amplitude is proportional to an amplitude of a second current supplied by the constant current generators through the duty cycle of the first current.

Abstract: A sense amplifier of the type coupled to a reference bit line and at least one cell array bit line. The sense amplifier includes an amplifying stage and a current voltage conversion circuit that compare a reference current from the reference bit line and a cell current from the cell array bit line. The current-voltage conversion circuit includes a voltage setting circuit for setting predetermined voltages on the reference bit line and the cell array bit line, a load circuit for the reference bit line and the cell array bit line, and current mirror circuits for mirroring the reference current and the cell current into the amplifying stage. The load circuit for the reference bit line and the current mirror circuit for the reference current are different circuits, and the load circuit for the reference bit line includes a transistor that mirrors a predetermined current that is generated outside of the sense amplifier.

Abstract: An analog-to-digital converter (500) for sampling high speed video signals includes a first input (502) for receiving an electronic signal, a sampling clock input (547) for receiving a sampling clock signal, and first and second sampling circuits. The first sampling circuit is arranged in a differential circuit arrangement, and is electrically connected to the first input (502) and to the sampling clock input (547) and is responsive to the sampling clock signal, for sampling the electronic signal to provide a pair of boundary reference voltage signals (706, 708, 710, 712) that bound the voltage of the sampled electronic signal, and further to convert the sampled electronic signal to provide the most significant bits (554) of a digital representation of the electronic signal at times indicated by the sampling clock signal.

Abstract: A semiconductor memory cell having a word line, a bit line, a precharge line, an access transistor, and first and second cross-coupled inverters. The first inverter includes a first P-channel transistor and a first N-channel transistor, and the second inverter includes a second P-channel transistor and a second N-channel transistor. The access transistor selectively couples the bit line to an output of the first or second inverter, and one terminal of the first N-channel transistor is connected to the precharge line. In a preferred embodiment, a control circuit is provided that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line. A method of writing data to a semiconductor memory cell that is coupled to a word line and single bit line is also provided.

Abstract: A method for designing a processor core is provided. Configuration registers are programmed by providing a cell configured at either one or zero for each bit of the configuration registers. Each configured cell is a latch with a data input and control signal inputs for receiving a direct resetting command and a direct setting command, and is configured at either one or zero by inhibiting either the direct resetting command or the direct setting command. Further, writing into the cells is permitted only in a test mode. Also provided is a method for designing and programming a processor core of the type having configuration registers. According to this method, a non-programmed processor core is designed by providing one vacant cell for each bit of the configuration registers. The vacant cell has the same abstract as both cells configured at one and cells configured at zero.

Abstract: A method is provided for controlling a capacitive charge pump. The charge pump is regulated by a regulating voltage when the supply voltage is greater than the regulating voltage. When the supply voltage is less than a triggering voltage, which is less than or equal to the regulating voltage, the charge pump is automatically supplied between the supply voltage and ground. In one preferred method, the charge pump has a first supply terminal connected to the supply voltage and a second supply terminal that is automatically grounded when the supply voltage is less than the triggering voltage. Also provided is a capacitive charge pump device that includes a charge pump having first and second supply terminals, a voltage regulator delivering a regulating voltage, a switch connected between the second supply terminal and ground, and switch control circuitry for automatically controlling the switch.

Abstract: A method is provided for forming an on-screen display (OSD) for overlay on a video image. According to the method, colors that are to be used to display the OSD are stored in a color look-up table, and a coefficient of transparency is assigned to each line of pixels of the OSD before overlaying the OSD on the video image. In a preferred method, the colors are stored in the color look-up table as three significant values representing chrominance and luminance for each pixel of the OSD, and the assigned coefficients of transparency are stored in a programmable register. This provides a substantial memory space gain in the color look-up table, and thus the range of available colors can be very wide. A device for forming an OSD for overlay on a video image is also provided. The device includes a color look-up table that stores a color for each pixel of the OSD, and a transparency programming register that assigns a transparency level to each line of pixels of the OSD.

Abstract: A method for reducing disturbing effects of coupling between a first transmission/reception device and a second transmission/reception device that are each connected to a subscriber line. According to the method, a signal received on a reception path of the first device is delayed by a delay equal to p times the transmission period. A coupling signal relating to a transmission path of a second device and the reception path of the first device is estimated based on a signal transmitted over the transmission path of the second device, and the delayed signal is ridded of the estimated coupling signal. Additionally, a device for transmitting/receiving a signal is provided. The device includes a memory coupled to a reception path for temporarily storing p symbols, a subtraction circuit, and a coupling estimation block.

Abstract: An operational amplifier is provided that includes an inverting input channel, a non-inverting input channel, and an output stage. Each of the input channels controls at least one input transistor, and the output stage supplies an output voltage as a function of a potential difference at the input channels. Additionally, the operational amplifier includes at least one signal correction element in association with at least one of the input channels. The signal correction element is selectively put into circuit to selectively add an offset voltage correction signal to a signal that is supplied to the output stage in order to balance the characteristics of the two input channels. Also provided is a circuit for correcting the offset voltage of an operational amplifier.

Abstract: A process for fabricating a metal-metal capacitor within an integrated circuit comprises the steps of: producing a first metal electrode, a second metal electrode, and a dielectric layer on top of a lower insulating layer; and depositing an upper insulating layer on top of the two metal electrodes and the dielectric layer. The integrated circuit comprises the insulating layer, a first metal layer which is on top of the lower insulating layer, and the upper insulating layer which is on top of the first metal layer. The capacitor comprises the first metal electrode, the second metal electrode, and the dielectric layer wherein each of the two metal electrodes is in contact with one side of the dielectric layer. The electrodes and the dielectric layer lie between the lower insulating layer, which supports a level of metallization (M1), and the upper insulating layer which covers this level of metallization.

Abstract: An integrated circuit is provided that includes a first internal circuit using a first internal clock signal whose first edges are active. The first internal circuit includes a test cell having an input and an output, a first transmission line connected to the input of the test cell, and a second transmission line connected to the output of the test cell. The test cell includes first and second latches and a selection circuit. The first latch stores either information on the first transmission line or information received from another test cell, and the second latch selectively receives the information stored in the first latch. The selection circuit provides to the second transmission line either the information on the first transmission line or the information stored in the second latch. The test cell also includes means for storing the information on the first transmission line in the second latch during second edges of the first internal clock signal when the test cell is not in test mode.