Abstract: In a delay measuring circuit (10), an input clock signal (13) is applied to a multitapped delay line (14), the output taps of which are connected to a switch (26) which selects one of the switch inputs for connection to a phase comparator (34) which compares the input clock signal (13), delayed in a delay device (38) to compensate for the delay inherent in the switch (26), with the output of the switch (26). The input clock signal is also applied to a counter (22), and when the phase comparator (34) detects a phase match, the counter value is stored in a latch (32), the counter (22) is reset to a predetermined value, and the counting procedure resumed. The latch (32) thus always stores a value dependent on the delay of an individual delay cell (16-l to 16-N). This stored value can be applied to various uses, such as in a timing watchdog circuit or for generating accurate delays.

Abstract: A data synchronizer that operates at two to four times greater clock and data rates than previous data synchronizers. By using a positive feedback, self latching gate as the first memory element, rather than a cross-coupled device such as a flip-flop, such rates are attained without inducing metastable oscillation. The positive feedback, self latching gate is far less prone to metastable oscillation since it does not have two cross-coupled devices fighting each other to resolve the proper response to an input. Instead, the self latching gate latches up if a data HIGH is present during a clock HIGH, and remains LOW otherwise. External circuitry resets the self latching gate to the LOW state before the start of each clock HIGH cycle to remove any previous latched state. The self latching gate output is then synchronously sampled by a type D flip-flop to provide a completely synchronized data output.

Abstract: A converter circuit for converting binary logic signals from a CMOS circuit into binary signals for an ECL circuit. Two output transistors in the converter circuit are connected in parallel between the V.sub.DD CMOS supply voltage and the output of the converter circuit. The resistance across the drain-to-source terminals of the output transistors form a voltage divider network with a pulldown resistor in the ECL circuit. In one embodiment, one of the output transistors is enabled by a logic "1" from the CMOS circuit and the other is enabled only by a logic "0". In another embodiment, one output transistor is always enabled and the other is enabled only by a logic "0" from the CMOS circuit. In both embodiments, the effective resistance across the parallel transistors is different for a logic level "1" and a logic level "0", so that the voltage at the output is also different.

Abstract: An electronic circuit for converting trinary level input signals on a first line into binary level signals on two or more output lines using contemporary CMOS field effect transistor integrated circuits. According to one embodiment, conversion is accomplished using two CMOS inverters each asymmetrically configured to exhibit transconductances which differ by a factor in excess of 5. In another form, the circuit provides hysteresis through positive feedback to limit binary output state perturbations attributable to trinary signal level input noise. The invention also encompasses the use of decode logic and logically combined delay elements to eliminate "glitches" and facilitate selective enablement of the decoded states representing the intermediate of the trinary input levels.

Abstract: An improved cable connector locking arrangement suitable for D-shell connectors eliminates the standoffs and threaded knobs in standard design and replaces them with tabbed, resilient flanges which snap in place for quick mating and locking of the D-shell connectors. Release bars in the preferred embodiment displace the flanges and hence tabs away from their mating surface for unlocking and disconnection of the connectors.

Abstract: A control circuit and method for regulating the current flow through a series connected inductor and transistor. The circuit comprises an operational amplifier for receiving a first voltage proportional to the current flow, for receiving a variable second voltage, and for providing a control current to the transistor which keeps the transistor out of its saturation region.

Abstract: A transient immune bistable input buffer circuit. The circuit comprises a filter connected between an input and a reference voltage terminal to the circuit for reducing the sensitivity of the circuit to a voltage transient on the terminal.

Abstract: A wireless local area network (10) includes a plurality of stations (12) adapted to transmit and receive message packets via a distribution system (30). In a time division multiplexing embodiment the network (10) operates using successive timing frames (FR1, FR2, etc.) each consisting of three timing intervals (T1, T2, T3). During the first timing interval (T1) the distribution system (30) normally transmits synchronizing packets (HBT), to which a station (12) desiring to transmit responds by transmitting an information packet during the next second timing interval (T2). During the subsequent first timing interval (T1), the distribution system (30) retransmits the received information packet.

Abstract: A cryogenically cooled integrated circuit apparatus is disclosed. The apparatus includes a cryogenic vessel with an integrated circuit package positioned in an opening at one end. One face of the integrated circuit is in direct contact with cryogenic fluid and a second face has a standard pin array which is connectable to a printed circuit board.

Abstract: A converter circuit for converting signals from a non-CMOS circuit into signals for a CMOS circuit. A level shifter stage in the circuit has a first MOS transistor for receiving at its gate the non-CMOS signals which always enable the first transistor and a second MOS transistor for receiving at its gate a constant voltage for enabling the second transistor. Since these transistors do not switch between non-enabling and enabling conditions in order to change the logic levels at the output of the converter circuit, the circuit operates quickly. In one embodiment the converter circuit converts ECL signals into CMOS signals, and in a second embodiment the converter circuit converts TTL signals into CMOS signals.

Abstract: In a high speed digital computer data transfer system, data bus voltage swings between logic high and logic low levels are reduced by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. The output voltages are converted to the proper logic levels with the aid of a differential (sense) amplifier. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

Abstract: A low current output driver for a gate array. The driver has first and second reference voltage sources, a first transistor of a first conductivity type, and a plurality of second transistors of a second conductivity type. The first transistor is connected between the first reference voltage source and the output. The second transistors are series connected between the first and second reference voltage sources. The control electrode of the first transistor is connected to a common point between two of the second transistors. At least one of the second transistors is diode connected to provide an intermediate voltage to the control electrode of the first transistor, thereby reducing the output current flow.

Abstract: Methods and apparatus for lowering integrated circuit (IC) chip ambient temperatures allow a slow IC chip to simulate a faster, functionally equivalent one for design testing purposes when the faster chip is not yet available. The cooling devices employed include a cryogenic chip cooling apparatus, and a novel thermo-electric chip cooling apparatus using a directly water-cooled Peltier effect device attached to the surface of the IC chip.

Abstract: A method and apparatus for sensing the amount of current data traffic on a high speed parallel bus, such as a Multibus II, and dynamically adjusting the allowable length of a any data block from any bus agent to optimize bus efficiency. A data transfer activity counter or similar device counts the amount of bits transferred in a predetermined sample interval, which is decoded after every sample interval and the allowable block length adjusted. The data block lengths are preselected to optimize efficiency at various average operating conditions with the further consideration that each agent has a maximum data latency time which should not be exceeded before that agent gains access to the bus.

Abstract: A random access memory (RAM) device capable of performing logic combinations of new and previously stored data in a single memory access cycle. In contrast to conventional RAM data combination sequences, which involve a succession of read-modify-write cycles, the present architecture implements logical combinations of new RAM data with old RAM data during a single access cycle. In a preferred arrangement, decoding logic combines the new data with mode select signals to generate a set of FORCE 1, FORCE 0, COMP and NOOP control signals. The control signals regulate the bit line sense amplifier and logic to allow direct interaction with the bit line data during RAM addressing. The invention is particularly useful in graphic video display systems frame buffers where rapid pattern changes are difficult to implement using moderate speed and cost RAM devices.

Abstract: In a high speed complementary metal-oxide-semiconductor (CMOS) inter-integrated circuit (IC) chip communication system, transmission line voltage swings between logic high and logic low levels are reduced by defining minimum and maximum bus voltages which lie between CMOS logic levels, thus lowering bus transition and hence data transfer times. The system is versatile, and does not involve typical emitter-coupled logic (ECL) logic levels. Transceivers interfacing between IC chips and the backpanel transmit data in the reduced logic level range on a pre-charged transmission line, and receive and convert data back to CMOS levels. A limiting transistor in the transmitter portion of the transceiver limits logic low level of the transmission line. The receiver portion of the transceiver converts the voltages received to CMOS levels with the aid of a differential (sense) amplifier.

Abstract: An integrated circuit driver for high and low lines in a bus. The driver comprises first and second current sources connected to high and low voltage sources, respectively, and first and second transistor circuits for blocking voltage spikes higher or lower than the voltages provided by the high and low voltage sources. The first current source and the first transistor circuit are series connected between the high voltage supply and the high line, and the second current source and the second transistor circuit are series connected between the low voltage source and the low line.

Abstract: A standoff and retainer for use in mechanically and electrically connecting two or more printed circuit boards in a parallel spaced type arrangement. The metallic standoff is constructed in the form of a sleeve partially closed at one end. The plastic retainer is also formed in the shape of a sleeve but includes a male connector at one end. The standoff is attached to a printed circuit board by advancing the connector end of the retainer into the open end of the standoff until the connector snaps into engagement with the hole in the partially closed end wall of the standoff and a mounting hole in the printed circuit board.

Abstract: A cable or wire (information bus, power supply, etc.) carrying method and apparatus for modular computer cabinets and the like in which the cabinet frame end walls have notch-like voids. The notches, preferably on the rear side of the cabinets are nearly fully enclosed, save a small opening (to preserve structural integrity) through which the cables may enter. The openings are covered by closure members and decorative trims once the cable is in place. The result is a modular computer system without unsightly wires, and in which the modules may be easily and quickly inserted or removed without the need for dismantling the cable attached to the backs of the other modules.

Abstract: An analog-to-digital inverter includes successive approximation control logic for generating ten-bit binary numbers, a digital-to-analog converter (DAC) having a resistor string and a weighted-capacitor array for converting the ten-bit binary output of the control logic to a known analog voltage, and an analog comparator for comparing the output of the DAC to a reference voltage provided via a tap to the mid-point of the DAC resistor string. The unknown analog voltage input to the ADC and the reference voltage are provided to the capacitor array to precharge the array to a voltage equal to the reference voltage minus the unknown analog voltage. The output of the DAC is therefore equal to the known analog voltage plus the reference voltage minus the unknown analog voltage.