Abstract: The subject invention is a method for processing a plastic packaged electronic device with soldered leads. The solder has a critical temperature which if exceeded more than once results in its oxidation. The method comprises protecting the device with a carrier, and baking the device and carrier in a low pressure environment and at a temperature sufficiently high enough to drive off moisture previously absorbed by the plastic but lower than the critical temperature of the solder.

Abstract: A pin grid array package for carrying an integrated circuit chip having input/output leads. The pin grid array package includes a carrier having a centrally located opening for carrying the integrated circuit chip, a plurality of input/output pins spaced around the periphery of the centrally located opening, interconnect leads on the carrier for connecting selected ones of the input/output pins to selected leads of the integrated circuit chip, and heat sink material around the periphery of the input/output pins which serves as a cooling-fin for efficient integrated circuit chip heat removal. Each of the plurality of input/output pins is normal to the plane of the integrated circuit chip and extends through the carrier with a first portion extending away from a first side of the carrier and a second portion extending away from a second side of the carrier.

Abstract: A module for insulatively housing and refrigerating a semiconductor device which is designed to be plugged into a printed circuit board within a conventional air-cooled electronic system. The plug-in module is designed such that the semiconductor device within the module can be operated at temperatures from -200.degree. C. down to the temperatures of liquid helium, while a short distance below the housing portion of the module the plug-in conductors connect to a connector on a conventionally cooled processor board. This is accomplished without frost or other type of troublesome moisture forming on the plug-in conductors.

Abstract: For LSI/VLSI integrated circuits which inherently have an address decoder and a data bus, a scan testing method and apparatus is presented which does not require additional pin connections to be dedicated for scan test implementation. Counter to the Joint Test Action Group approach, the present invention uses additional registers, multiplexers, and decoders in conjunction with the existing buses to provide test access to otherwise embedded layers of logic circuitry, without the addition of a single pin connection to a integrated circuit chip package. Further, since this test method and apparatus uses the data bus and registers just as the rest of the chip, slow and complex d.c. level shifting equipment is not required.

Abstract: A method is disclosed whereby individual members of a group of members or entities may be provided, under the control of a trusted member, referred to as the parent, with respective individual secret keys for use in public key cryptography, such that the matching public key can be readily derived, and group membership authenticated. The parent initially establishes a public key (e,N) where N=P.Q is the product of two primes. In response to a request from a group member, the parent selects two further primes R,S and communicates two values dependent thereon to the requesting member, which selects two more primes T and U for use in conjunction with the received values to establish the member's secret key.

Abstract: The subject invention is an interface circuit between a requesting device and a responding device. The circuit comprises a flip-flop responsive to a request signal received from the requesting device and a handshake signal received from the responding device to generate a control signal. The circuit also comprises a gate for receiving the control and handshake signals and generating an acknowledge signal. The removal of the request signal sets the control signal to a first value which disables the gate and removal of the handshake signal resets the control signal to a second value which enables the gate.

Abstract: An entity such as a smart card includes microprocessor means, input/output means, and PROM storage means which stores a set of transformations S.sub.i (i=1, . . . , n) of a corresponding set of public factors F.sub.1 (i=1, . . . , n), where S.sub.i =F.sub.i.sup.d (mod N), d being the secret key counterpart of a public key e associated with the modulus N, which is the product of two primes. An authentication device which stores the public factors F.sub.i and the values of N and e, generates an n bit random vector v=v.sub.i which is transmitted to the card where a product Y of the values S.sub.i selected according to the 1 bits of v is computed and transmitted to the authentication device which computes X.sub.act =Y.sup.e (mod N) and also computes X.sub.ref, the product of the F.sub.i selected according to the 1 bits of v. If X.sub.act and X.sub.ref are equal, then the card is authenticated to within a certain probability. An analogous method is disclosed for certifying messages to be transmitted.

Abstract: A new integrated circuit for interfacing a standard IEEE 796 bus to a VSB-type buffer bus. This integrated circuit includes a DMA channel for high speed access of the IEEE 796 bus to the buffer bus, and a slave bus channel for high speed access of the buffer bus to the IEEE 796 bus. A third bus interface connects to a local processor to assist in arbitration and control during some types of data transfers.

Abstract: The subject invention is a circuit and method of providing the sum of first and second n bit binary numbers having a difference of one or less. The method comprises combining the least significant bits of the numbers in a first coincidence gate to provide the least significant bit of the sum, combining the nth and (n-1)st bits of the numbers in a first logic network to provide the most significant bit of the sum, and combining solely the ith and (i-1)st bits of the numbers in an ith logic network to provide the ith bit of the sum, for all values of i where 1<i<n+1.

Abstract: A circuit for regulating the output voltage of a switched mode power supply having a current mode magnetic amplifier includes a current transformer for sensing current flow through the magnetic amplifier. The sensed current is provided to a circuit which includes a resistor for developing a pulsating voltage and a storage capacitor for converting the pulsating voltage to a tracking voltage and storing the tracking voltage. The tracking voltage and a reference voltage are provided to a differential amplifier, the output of which operates a transistor which controls the operation of the magnetic amplifier, thereby regulating the output voltage of the power supply.

Abstract: The subject invention is a device for joining and separating first and second printed circuit boards connectable by a socket on one of the boards and a plurality of pins projecting from the other of the boards. The device comprises a screw held captive to the first board but rotatable therein, and a spacer fastened to the second board and having a threaded hole for receiving the screw. The pins are inserted into and withdrawn from the socket by the engagement and disengagement, respectively, of the threaded hole by the screw.

Abstract: A switch mode power supply includes an AC to DC converter, a pulse width modulator for generating a series of pulses to control the switching of the DC across the primary winding of a transformer, and a start-up circuit connecting the AC to a power input of the pulse width modulator. A thermistor provides thermal protection for converter and start-up circuit components during abnormal operation, and a switch for disconnecting the start-up circuit and bypassing the thermistor after the power supply has been started improves power supply efficiency by eliminating power loss through the start-up circuit and thermistor.

Abstract: A circuit for the stable synchronization of an asynchronous data signal. The circuit comprises a first latch for receiving a first asynchronous data signal, a first delayed system clock signal, and a synchronized reset signal and for providing a system clock synchronized version of the first asynchronous data signal. A first delaying circuit receives a system clock signal and the first asynchronous data signal and provides the first delayed system clock signal. The circuit also includes a second latch for receiving a second asynchronous data signal which is a function of the inverse of the first asynchronous data signal and a second delayed system clock signal, and for providing the synchronized reset signal. A second delaying circuit receives the system clock signal and the first asynchronous data signal and provide the second delayed system clock signal.

Abstract: A printed circuit board assembly is disclosed which includes a number of rigid printed circuit boards connected by a number of flexible printed circuit panels. Integrated circuits and similar components are mounted on the rigid printed circuit boards. The components are interconnected by printed circuit conductors of the rigid printed circuit boards and the flexible printed circuit panels. The resulting board assembly can provide a manifold increase in the usable component area over a single flat, rigid printed circuit board when it is folded and installed into a standard cylindrical, coolant filled container.

Abstract: A data transmission system for transferring data signals between first and second buses is disclosed. The system includes means attached to the buses for the transfer of data signals to the buses and supply means connected to the buses for precharging the buses to a first voltage level. The system also includes circuit means connecting the buses and responsive to a data signal at a second voltage level on either of said buses for transferring the signal to the other bus.

Abstract: A single chip cache address comparator with an on-chip static RAM for storing and checking the cache tags of an external cache memory. This cache address comparator has a built-in incrementing counter which controls the burst fill of the internal cache of a 68020/68030 microprocessor from the associated external cache memory within the required five processor clock cycles. Further, additional on-chip control logic is provided to control the 68020/68030 system buses to coordinate a burst fill operation.

Abstract: An interlock switch for the service door of a computer. The switch prevents power from being automatically resupplied to the computer if the door is opened while power has been interrupted, even if the door is subsequently closed. The interlock switch includes a magnetic reed switch, an electromagnet for closing the reed switch contacts when the power-on switch of the computer is actuated, and a permanent magnet which holds the reed switch contacts closed as long as the service door has not been opened. The reed switch and electromagnet are mounted on the frame of the cabinet of the computer. The permanent magnet is mounted on the edge of the service door adjacent the reed switch. The use of the switch in a security system is also disclosed.

Abstract: A simple, inexpensive and reliable dispensing system for a cryogenic fluid is presented. The system controls the dispensing of a cryogenic liquid, such as liquid nitrogen, from a large, well insulated reservoir to a cooling enclosure for an electronic circuit or similar enclosure. In order to prevent a considerable heat influx from the environment to a standing cryogenic fluid through long lengths of insulated conduit between the main, well insulated reservoir and the enclosure, the system fills an intermediate reservoir and subsequently drains most of the long lengths of insulated conduit into the intermediate reservoir by a siphon action. The intermediate reservoir is well insulated and holds enough cryogenic fluid to fulfill the requirements of the cooling enclosure for long periods of time before refill from the main reservoir is necessary.

Abstract: An inversion coupler for use in a computer system is disclosed. The computer system has a backpanel with a front side for the mounting of printed circuit boards each with a plurality of rows of connector pins. The inversion coupler mounts one of the printed circuit boards to the back side of the backpanel. The inversion coupler comprises first and second connector bodies. The first body is engageable with the pins of the board mountable to the back side and the second body is connectable to the pins of a board mountable to the front side. Each of the connector bodies has a plurality of IC pins arranged in a plurality of mutually corresponding rows. The pins in each row are connected to the pins in the corresponding row in inverse order.

Abstract: The subject invention is an ECL to CMOS converter for converting high or low ECL logic signals. The converter comprises a CMOS inverter for providing low or high CMOS logic signals at its output in response to a first or second signal, respectively, applied to its input. The first signal must exceed a first predetermined value and the second signal must fall below a second predetermined value. The first and second predetermined values are such that either the low ECL signal does not fall below the second predetermined value or the high ECL signal does not exceed the first predetermined value. The converter also provides means for converting the high and low logic signals to the first and second signals, respectively.